CP3SP33SMSSLASHNOPB datasheet(257/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

26.8 DMA Support

Each CVSD/PCM converter has four DMA channels for processor independent operation. Both receive

and transmit for CVSD data and PCM data can be enabled individually. A CVSD/PCM module asserts a

DMA request to the on-chip DMA controller under the following conditions:

•

The DMAPO bit is set and the PCMOUTn register is full, because it has been updated by the converter

core with a new PCM sample. (The DMA controller can read out one PCM data word from the

PCMOUTn register.)

•

The DMAPI bit is set and the PCMINn register is empty, because it has been read by the converter

core. (The DMA controller can write one new PCM data word into the PCMINn register.)

•

The DMACO bit is set and a new 16-bit CVSD data stream has been copied into the CVSD Out FIFO.

(The DMA controller can read out one 16-bit CVSD data word from the CVSD Out FIFO.)

•

The DMACI bit is set and a 16-bit CVSD data stream has been read from the CVSD In FIFO. (The

DMA controller can write one new 16-bit CVSD data word into the CVSD In FIFO.)

The DMA controller only supports indirect DMA transfers. Therefore, transferring data between a

CVSD/PCM module and another on-chip module requires two bus cycles.

The trigger for DMA may also trigger an interrupt if the corresponding enable bits in the CVCTRLn register

is set. Therefore, care must be taken when setting the desired interrupt and DMA enable bits. The

following conditions must be avoided:

•

Setting the PCMINT bit and either of the DMAPO or DMAPI bits.

•

Setting the CVSDINT bit and either of the DMACO or DMACI bits.

Because the PCM I/O DMA requests can be handled by either the CPU or DSP DMA controllers, the DMA

requests are passed through the Audio Subsystem Controller (ASC), which is programmed to route them

to the DMA controller. To use the PCM I/O DMA requests, they must be enabled at three levels:

•

CVSD/PCM module—the PCM I/O DMA requests must be enabled using the DMAPI and DMAPO bits

in the CVCTRLn registers.

•

ASC module—the PCM I/O DMA requests are assigned to ASC DMA channels 3 (PCMIN0), 2

(PCMOUT0), 5 (PCMIN1), and 4 (PCMOUT1). These channels are controlled by bits 3, 2, 5, and 4,

respectively, in the ASCDMASEL0 register. The bits must be clear to select the CPU DMA controller or

set to select the DSP DMA controller. If the DSP DMA controller is selected, the DSP DMA channel

must be enabled in the ASCDDMASELn registers.

•

DMA controller—the DMA requests must be enabled in the DMA controller. For the CPU DMA

controller, these are DMA requests 3 (PCMIN0), 2 (PCMOUT0), 5 (PCMIN1), and 4 (PCMOUT1).

The CVSD I/O DMA requests are only provided to the CPU DMA controller.

26.9 CVSD/PCM Audio Data Flow

CVSD and PCM data can be transferred to and from the CVSD/PCM modules using DMA channels.

Alternatively, CVSD data can be transferred to and from the CVSD/PCM modules by software directly

accessing the FIFOs, through the CVSDINn and CVSDOUTn registers.

The CVSDOUT and CVSDIN DMA channels are linked to the operation of the CVSD/PCM module internal

FIFOs. Each time the CVSDOUT FIFO reaches its almost full level of 5 entries, a DMA request is

generated. Initially when the CVSDIN FIFO contains 3 or fewer entries, a single DMA transfer is

requested. Further DMA requests are generated each time the CVSD In FIFO is read by the CVSD/PCM

converter.

Three of the four AAI channels are supported by independent DMA channels for both the receive and

transmit data paths. Figure 26-2 shows the flow of audio data when both CVSD/PCM modules are used to

support data exchange between the Bluetooth LLC and two external codec channels accessed through

the AAI.

Dual CVSD/PCM Conversion Modules

257

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