CP3SP33SMSSLASHNOPB datasheet(252/407 Pages) TI1

252 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

TXLIRQ

The Transmit Left Channel Interrupt Request Pending bit is set when the

I2STXCTL.TXLI bit is set and the left channel transmit FIFO fill level falls below the

threshold specified in the I2STXCTL.TXFIFOTHRESH field. Once set, the TXLIRQ bit

remains set until cleared by writing 1 to the bit.

0 – Interrupt request deasserted.

1 – Interrupt request asserted.

TXERIRQ

The Transmit Error Interrupt Request Pending bit is set when the I2STXCTL.TXER bit is

set and either transmit FIFO has been underrun. Once set, the TXERIRQ bit remains

set until cleared by writing 1 to the bit.

0 – Interrupt request deasserted.

1 – Interrupt request asserted.

TXSTATUSL

The Transmit FIFO Status Left Channel field indicates the current fill level of the left

channel transmit FIFO. This field is not sticky, so an underrun condition may disappear

before software reads this field. Use the TXERIRQ bit to determine whether a FIFO

underrun has occurred. The TXST bit in the I2STXCTL register controls the

interpretation of this field.

TXSTATUSL FIELD

TXST BIT

DESCRIPTION

1Fh

Overrun error (written while full)

1Eh

Underrun error (read while empty)

00h to 08h

0 to 8 empty words

00h to 08h

0 to 8 filled words

RXRIRQ

The Receive Right Channel Interrupt Request Pending bit is set when the

I2SRXCTL.RXRI bit is set and the right channel receive FIFO fill level rises above the

threshold specified in the I2SRXCTL.RXFIFOTHRESH field. Once set, the RXRIRQ bit

remains set until cleared by writing 1 to the bit.

0 – Interrupt request deasserted.

1 – Interrupt request asserted.

RXLIRQ

The Receive Left Channel Interrupt Request Pending bit is set when the I2SRXCTL.RXLI

bit is set and the left channel receive FIFO fill level rises above the threshold specified in

the I2SRXCTL.RXFIFOTHRESH field. Once set, the RXLIRQ bit remains set until

cleared by writing 1 to the bit.

0 – Interrupt request deasserted.

1 – Interrupt request asserted.

RXERIRQ

The Receive Error Interrupt Request Pending bit is set when the I2SRXCTL.RXER bit is

set and either receive FIFO has been overrun. Once set, the RXERIRQ bit remains set

until cleared by writing 1 to the bit.

0 – Interrupt request deasserted.

1 – Interrupt request asserted.

RXSTATUSR

The Receive FIFO Status Right Channel field indicates the current fill level of the right

channel receive FIFO. This field is not sticky, so an overrun condition may disappear

before software reads this field. Use the RXERIRQ bit to determine whether a FIFO

overrun has occurred. The RXST bit in the I2SRXCTL register controls the interpretation

of this field.

RXSTATUSR FIELD

RXST BIT

DESCRIPTION

1Fh

Overrun error (written while full)

1Eh

Underrun error (read while empty)

00h to 08h

0 to 8 empty words

00h to 08h

0 to 8 filled words

252

I2S Interface

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB bảng dữ liệu(PDF) 252 Page - Texas Instruments

CP3SP33SMS/NOPB bảng dữ liệu(HTML) 252 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL