CP3SP33SMSSLASHNOPB datasheet(248/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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Reserved

WSRES

CLKDIV

Reserved

CLKSEL

CLKEN

The Clock Enable bit enables clock to the module.

0 – Module disabled.

1 – Module enabled.

CLKSEL The Clock Select field selects the clock source for the module.

00 – PCLK Clock.

01 – Auxiliary clock 5.

10 – Reserved.

11 – Reserved

The Master Select bit selects whether the interface is operating in master or slave mode.

0 – Slave mode.

1 – Master mode.

CLKDIV

The Clock Select field holds the divisor (expressed in half-periods of the clock source selected

by CLKSEL) for generating the I2S bus clock output I2SCLK in master mode. The field is

biased by 1, so the clock source is divided by ((CLKDIV + 1) ÷ 2) to obtain I2SCLK. Zero is a

reserved value for this field.

WSRES

The Word Select Resolution field specifies the length of one phase (one-half period) of the

word select output I2SSWS in master mode. The length is specified in terms of I2S bus clock

output I2SCLK periods. The field is biased by 1, so the default value of 7 results in a length of

8 clock periods. This field is only defined for values from 00111b to 11111b.

25.3.2 I

2S Receiver Control Register (I2SRXCTL)

The I2SRXCTL register is a 32-bit, read/write register that controls the I2S receiver. At reset, this register

is initialized to 0000 001Ch.

Reserved

RXLD

RXRD

RXLI

RXRI

RXER

RXRES

RXMOD

Reserved

RXST

Reserved

RXFIFOTHRESH

RXALIGN

RXMOD

The Receiver Mode field selects the format used by the receiver.

00 – Receiver disabled.

01 – I2S format.

10 – Left-justified format.

11 – Right-justified format.

RXRES

The Receiver Resolution field specifies the number of data bits to receive. In right-justified

mode, this field also controls data alignment. It is particularly important to set RXRES

correctly in right-justified mode, otherwise the MSB of the received serial data will not be

aligned. For I2S- and left-justified modes, data will always be correctly aligned (MSB in the

correct position), however if RXRES specifies fewer data bits than are available on the bus,

the LSBs will be truncated. The field is biased by 1, so the default value of 7 results in 8

bits. This field is only defined for values from 00111b to 10111b.

RXER

The Receive Error bit enables the error interrupt from the receiver. A receive error occurs

when the receiver attempts to load data into a full FIFO for the left or right channel. The

status of the error condition is indicated by the RXERIRQ bit in the I2SSTAT register.

0 – Interrupt disabled.

1 – Interrupt enabled.

248

I2S Interface

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