CP3SP33SMSSLASHNOPB datasheet(247/407 Pages) TI1

247 / 407 page

Mode

Bits 31:24

Bits 23:16

Bits 15:8

Bits 7:0

Data

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

Error interrupts may be enabled for receive FIFO overrun and transmit FIFO underrun. A receive FIFO

overrun occurs on writing to a full receive FIFO. A transmit FIFO underrun occurs on reading from an

empty transmit FIFO. The RXER bit in the I2SRXCTL register enables receive error interrupts, and the

TXER bit enables transmit error interrupts.

To avoid a transmit FIFO underrun, the TXFIFOENL and TXFIFOENR bits allow enabling the transmit

FIFOs for loading before enabling the transmitter. However, as soon as the I2SCLK and I2SSWS signals

are active, the right transmit FIFO is drained. In slave mode, these signals can be disabled in the GPIO

registers until transmission is required. In master mode, the MS bit can be used to control the signals.

25.2 Data Alignment

Four alignment modes are available for the data registers, as shown in Figure 25-4. The RXALIGN field in

the I2SRXCTL register specifies the receiver mode, and the TXALIGN field in the I2STXCTL register

specifies the transmitter mode. If the receiver format has more bits than the mode, the least significant bits

are truncated. If the transmitter format has more bits than the mode, the least significant bits are padded

with the value in the LSBFILL bit.

Figure 25-4. Data Register Alignment Modes

25.3 I

2S Interface Registers

Table 25-1 lists the registers in the I2S interface.

Table 25-1. I2S Interface Registers

NAME

ADDRESS

DESCRIPTION

I2SCLK

FF 4000h

I2S Clock Register

I2SRXCTL

FF 4004h

I2S Receiver Control Register

I2STXCTL

FF 4008h

I2S Transmitter Control Register

I2SSTAT

FF 401Ch

I2S Status Register

I2SRXDATALEFT

FF 4014h

I2S Receiver Left Channel Data Register

I2SRXDATARIGHT

FF 4018h

I2S Receiver Right Channel Data Register

I2STXDATALEFT

FF 400Ch

I2S Transmitter Left Channel Data Register

I2STXDATARIGHT

FF 4010h

I2S Transmitter Right Channel Data Register

25.3.1 I

2S Clock Register (I2SCLK)

The I2SCLK register is a 32-bit, read/write register that controls clock configuration, master/slave select,

and word length. Before enabling master mode (MS bit = 1), the CLKSEL, CLKDIV, and WSRES

fields must be loaded. These fields can only be loaded in slave mode (MS bit = 0), so after enabling

master mode, the interface must be returned to slave mode to change any of their values. At reset, this

247

I2S Interface

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB bảng dữ liệu(PDF) 247 Page - Texas Instruments

CP3SP33SMS/NOPB bảng dữ liệu(HTML) 247 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL