CP3SP33SMSSLASHNOPB datasheet(245/407 Pages) TI1

245 / 407 page

I2SSCK

Left Channel

DS438

I2SSWS

I2SSDI,

I2SSDO

Right Channel

N-1

N-2

N-3

MSB

N-1

N-2

N-3

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

Four 8-level FIFOs are provided to buffer the receive and transmit directions of the two channels.

Programmable thresholds are provided to trigger interrupt or DMA requests when the FIFOs require

loading or unloading.

The I2S module provides a three-pin unidirectional or four-pin bidirectional serial interface consisting of:

•

Serial Clock (I2SCLK)—bit clock for serial data transfer. The transmitter drives the data on the falling

edge. The receiver latches the data on the rising edge. The bus master drives this signal.

•

Word Select (I2SSWS)—alternately selects between left and right channels, and defines the beginning

and end of a word. The high and low phases must be equal length. The bus master drives this signal.

•

Serial Data (I2SSDI and I2SSDO)—bit stream between the transmitter and receiver. The MSB is

always sent first. In the CP3SP33 implementation, separate pins are provided for serial data input

(I2SSDI) and serial data output (I2SSDO).

The I2S module supports three common audio interface formats:

•

I2S Format—MSB transmitted one clock period after I2SSWS toggles. I2SSWS is low for the left

channel and high for the right channel.

•

Left-Justified Format—MSB transmitted following the clock edge when I2SSWS toggles. I2SSWS is

high for the left channel and low for the right channel.

•

Right-Justified Format—LSB transmitted during the clock period before I2SSWS toggles. I2SSWS is

high for the left channel and low for the right channel.

The number of data bits is programmable from 8 to 24 bits per word, and the word length is programmable

from 8 to 32 bits. The data is positioned in the word according to the format. In the left-justified and I2S

formats, the data starts with the MSB in the first or second clock periods, respectively. If the word length is

less than the number of data bits, the trailing LSBs are truncated. In the right-justified format, the number

of data bits and the word length are used to determine when to start sending or receiving the data bits, so

it is critical to program these values correctly. In this format, the word length must be longer than the

number of data bits, otherwise the transceiver will default to left-justified mode.

Figure 25-1 shows the timing of an I2S format data transfer.

Figure 25-1. I2S Format

Figure 25-2 shows the timing of a left-justified data transfer.

245

I2S Interface

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