CP3SP33SMSSLASHNOPB datasheet(242/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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TXDSA BIT

SLOTS ENABLED FOR DMA

TXDSA0

TXDSA1

TXDSA2

TXFWL The Transmit FIFO Warning Level field specifies when a transmit interrupt is asserted. A

transmit interrupt is asserted when the number of bytes or words in the transmit FIFO is equal

or less than the warning level value. A TXFWL value of Fh means that a transmit interrupt is

asserted if one or more bytes or words are available in the transmit FIFO. At reset, the TXFWL

field is loaded with Fh.

24.7.9 Audio Clock Control Register (ACCR)

The ACCR register is used to control the bit timing of the audio interface. After reset, this register is clear.

8 7

BCPRS

FCPRS

CSS

The Clock Source Select bit selects one out of two possible clock sources for the audio

interface.

0 – Auxiliary Clock 1.

1 – Auxiliary Clock 8.

FCPRS The Frame Clock Prescaler is used to divide the bit clock to generate the frame clock for the

receive and transmit operations. The bit clock is divided by (FCPRS + 1). After reset, the

FCPRS field is clear. The maximum allowed bit clock rate to achieve an 8 kHz frame clock is

1024 kHz. This value must be set correctly even if the frame sync is generated externally.

BCPRS The Bit Clock Prescaler is used to divide the audio interface clock (selected by the CSS bit) to

generate the bit clock for the receive and transmit operations. The audio interface input clock is

divided by (BCPRS + 1). After reset, the BCPRS7:0 bits are clear.

24.7.10 Audio DMA Control Register (ADMACR)

The ADMACR register is used to control the DMA support of the audio interface. In addition, it is used to

configure the automatic transmission of the audio control bits. After reset, this register is clear.

13 12

11 10

8 7

4 3

Reserved

ACO

ACD

TMD

RMD

The Receive Master DMA field specify which slots (audio channels) are supported by DMA, i.e.,

when a DMA request is asserted to the DMA controller. If the RMDn bit is set for an assigned

slot (RXDSAn = 1), a DMA request is asserted when the ARDRn register is full. If the RXDSAn

bit for a slot is clear, the RMDn bit is ignored. The following table shows the receive DMA

request scheme.

RMD

DMA REQUEST CONDITION

0000

None

0001

ARDR0 full

0010

ARDR1 full

0011

ARDR0 full or ARDR1 full

x1xx

Not supported on CP3SP33

1xxx

242

Advanced Audio Interface

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