CP3SP33SMSSLASHNOPB datasheet(239/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

RXIC

The Receive Interrupt Enable bit controls whether receive interrupts are generated. If the

RXIE bit is clear, no receive interrupt will be generated.

0 – Receive interrupt disabled.

1 – Receive interrupt enabled.

RXEIE

The Receive Error Interrupt Enable bit controls whether receive error interrupts are generated.

Setting this bit enables a receive error interrupt, when the Receive Buffer Overrun (RXOR) bit

is set. If the RXEIE bit is clear, no receive error interrupt will be generated.

0 – Receive error interrupt disabled.

1 – Receive error interrupt enabled.

TXIE

The Transmit Interrupt Enable bit controls whether transmit interrupts are generated. Setting

this bit enables a transmit interrupt, when the Transmit Buffer Almost Empty (TXAE) bit is set.

If the TXIE bit is clear, no interrupt will be generated.

0 – Transmit interrupt disabled.

1 – Transmit interrupt enabled.

TXEIE

The Transmit Error Interrupt Enable bit controls whether transmit error interrupts are

generated. Setting this bit to 1 enables a transmit error interrupt, when the Transmit Buffer

Underrun (TXUR) bit is set. If the TXEIE bit is clear, no transmit error interrupt will be

generated.

0 – Transmit error interrupt disabled.

1 – Transmit error interrupt enabled.

RSIP

The Receive Interrupt Pending bit indicates that a receive interrupt is currently pending. The

RXIP bit is cleared by writing a 1 to the RXIC bit. The RXIP bit provides read-only access.

0 – No receive interrupt pending.

1 – Receive interrupt pending.

RXEIP

The Receive Error Interrupt Pending bit indicates that a receive error interrupt is currently

pending. The RXEIP bit is cleared by writing a 1 to the RXEIC bit. The RXEIP bit provides

read-only access.

0 – No receive error interrupt pending.

1 – Receive error interrupt pending.

TXIP

The Transmit Interrupt Pending bit indicates that a transmit interrupt is currently pending. The

TXIP bit is cleared by writing a 1 to the TXIC bit. The TXIP bit provides read-only access.

– No transmit interrupt pending.

1 – Transmit interrupt pending.

TXEIP

Transmit Error Interrupt Pending. This bit indicates that a transmit error interrupt is currently

pending. The TXEIP bit is cleared by software by writing a 1 to the TXEIC bit. The TXEIP bit

provides read-only access.

0 – No transmit error interrupt pending.

1 – Transmit error interrupt pending.

RXIC

The Receive Interrupt Clear bit is used to clear the RXIP bit.

0 – Writing a 0 to the RXIC bit is ignored.

1 – Writing a 1 clears the RXIP bit.

RXEIC

The Receive Error Interrupt Clear bit is used to clear the RXEIP bit.

0 – Writing a 0 to the RXEIC bit is ignored.

1 – Writing a 1 clears the RXEIP bit.

TXIC

The Transmit Interrupt Clear bit is used to clear the TXIP bit.

0 – Writing a 0 to the TXIC bit is ignored.

1 – Writing a 1 clears the TXIP bit.

TXEIC

The Transmit Error Interrupt Clear bit is used to clear the TXEIP bit.

0 – Writing a 0 to the TXEIC bit is ignored.

1 – Writing a 1 clears the TXEIP bit.

Advanced Audio Interface

239

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