CP3SP33SMSSLASHNOPB datasheet(237/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

ATDL

The Audio Transmit DMA Low Byte field holds the lower byte of the audio data.

ATDH

In 16-bit mode, the Audio Transmit DMA High Byte field holds the upper byte of the audio

data word. In 8-bit mode, the ATDH field is ignored.

24.7.5 Audio Global Configuration Register (AGCR)

The AGCR register controls the basic operation of the interface. The APB bus master has read/write

access to the AGCR register. After reset, this register is clear.

IEBC

FSS

IEFS

SCS

LPB

DWL

ASS

CLKEN

AAIEN

IOM2

IFS

FSL

CTF

CRF

ASS

The Asynchronous/Synchronous Mode Select bit controls whether the audio interface operates

in Asynchronous or in Synchronous mode.

0 – Synchronous mode.

1 – Asynchronous mode.

DWL

The Data Word Length bit controls whether the data word has a length of 8 or 16 bits.

0 – 8-bit length.

1 – 16-bit length.

LPB

The Loop Back bit enables the loop back mode. In this mode, the SRD and STD pins are

internally connected. After reset the LPB bit is clear, so by default the loop back mode is

disabled.

0 – Loop back mode disabled.

1 – Loop back mode enabled.

SCS

The Slot Count Select field specifies the number of slots within each frame. If the number of

slots per frame is equal to 1, the audio interface operates in normal mode. If the number of slots

per frame is greater than 1, the interface operates in network mode.

SCS

NUMBER OF SLOTS PER

MODE

FRAME

Normal mode

Network mode

IEFS

The Internal/External Frame Sync bit controls, whether the frame sync signal for the receiver

and transmitter are generated internally or provided from an external source.

0 – Internal frame synchronization signal.

1 – External frame synchronization signal.

FSS

The Frame Sync Select bit controls whether the interface (receiver and transmitter) uses long or

short frame synchronization signals.

0 – Short (bit length) frame synchronization signal.

1 – Long (word length) frame synchronization signal.

IEBC

The Internal/External Bit Clock bit controls whether the bit clocks for receiver and transmitter are

generated internally or provided from an external source.

0 – Internal bit clock.

1 – External bit clock.

Advanced Audio Interface

237

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