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CP3SP33SMS/NOPB bảng dữ liệu(PDF) 235 Page - Texas Instruments |
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CP3SP33SMS/NOPB bảng dữ liệu(HTML) 235 Page - Texas Instruments |
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235 / 407 page  CP3SP33 www.ti.com SNOSCW5 – MAY 2013 24.6.5 Loopback Mode In loopback mode, the STD and SRD pins are internally connected together, so data shifted out through the ATSR register will be shifted into the ARSR register. This mode may be used for development, but it also allows testing the transmit and receive path without external circuitry, for example during Built-In-Self- Test (BIST). 24.6.6 Freeze Mode When the Freeze mode is entered, the audio interface exhibits the following behavior: • The receive FIFO or receive DMA registers are not updated with new data. • The receive status bits (RXO, RXE, RXF, and RXAF) are not changed, even though the receive FIFO or receive DMA registers are read • The transmit shift register (ATSR) is not updated with new data from the transmit FIFO or transmit DMA registers. • The transmit status bits (TXU, TXF, TXE, and TXAE) are not changed, even though the transmit FIFO or transmit DMA registers are written. 24.7 Audio Interface Registers Table 24-1. Audio Interface Registers NAME ADDRESS DESCRIPTION ARFR FF 5000h Audio Receive FIFO Register ARDR0 FF 5004h Audio Receive DMA Register 0 ARDR1 FF 5008h Audio Receive DMA Register 1 ARDR2 FF 500Ch Audio Receive DMA Register 2 ARDR3 FF 5010h Audio Receive DMA Register 3 ATFR FF 5014h Audio Transmit FIFO Register ATDR0 FF 5018h Audio Transmit DMA Register 0 ATDR1 FF 501Ch Audio Transmit DMA Register 1 ATDR2 FF 5020h Audio Transmit DMA Register 2 ATDR3 FF 5024h Audio Transmit DMA Register 3 AGCR FF 5028h Audio Global Configuration Register AISCR FF 502Ch Audio Interrupt Status and Control Register ARSCR FF 5030h Audio Receive Status and Control Register ATSCR FF 5034h Audio Transmit Status and Control Register ACCR FF 5038h Audio Clock Control Register ADMACR FF 503Ch Audio DMA Control Register 24.7.1 Audio Receive FIFO Register (ARFR) The Audio Receive FIFO register shows the receive FIFO location currently addressed by the Receive FIFO Read Pointer (RRP). The receive FIFO receives 8-bit or 16-bit data from the Audio Receive Shift Register (ARSR), when the ARSR is full. In 8-bit mode, only the lower byte of the ARFR is used, and the upper byte contains undefined data. In 16- bit mode, a 16-bit word is copied from ARSR into the receive FIFO. The APB bus master has read-only access to the receive FIFO, represented by the ARFR register. After reset, the receive FIFO (ARFR) contains undefined data. Copyright © 2013, Texas Instruments Incorporated Advanced Audio Interface 235 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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