CP3SP33SMSSLASHNOPB datasheet(231/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

24.5.7.2 FIFO Operation

When a complete data word has been transmitted through the STD pin, a new data word is reloaded from

the transmit FIFO from the current location of the Transmit FIFO Read Pointer (TRP). After that, the TRP

is automatically incremented by 1. Therefore, the audio data to be transmitted in the next slot of the frame

is read from the next FIFO location.

A write to the Audio Transmit FIFO Register (ATFR) results in a write to the transmit FIFO at the current

location of the Transmit FIFO Write Pointer (TWP). After every write operation to the transmit FIFO, the

TWP is automatically incremented by 1.

When the TRP is equal to the TWP and the last access to the FIFO was a read operation (transfer to the

ATSR), the transmit FIFO is empty. When an additional read operation from the FIFO to the ATSR is

performed (while the FIFO is already empty), a transmit FIFO underrun occurs. In this case, the read

pointer (TRP) will be decremented by 1 (incremented by 15) and the previous data word will be

transmitted again. A transmit FIFO underrun is indicated by the TXU bit in the Audio Interface Transmit

Status and Control Register (ATSCR). No transmit interrupt will be generated (even if enabled).

If the current TRP is equal to the TWP and the last access to the FIFO was a write operation (to the

ATFR), the FIFO is full. If an additional write to the ATFR is performed, a transmit FIFO overrun occurs.

This error condition is not prevented by hardware. Software must ensure that no transmit overrun occurs.

The transmit frame synchronization pulse on the SFS pin and the transmit shift clock on the SCK pin may

be generated internally, or they can be supplied by an external source.

24.5.8 Receive

The receive shift register (ARSR) receives data words of all slots in the frame, regardless of the slot

assignment of the interface. However, only those ARSR contents are transferred to the receive FIFO or

DMA receive register which were received during the assigned time slots. A receive interrupt or DMA

request is initiated when this occurs.

24.5.8.1 DMA Operation

When a complete data word has been received through the SRD pin in a slot n, the new data word is

transferred to the corresponding receive DMA register n (ARDRn). A DMA request is asserted when the

ARDRn register is full. If a new slot n data word is received while the ARDRn register is still full, the

ARDRn register will be overwritten with the new data.

24.5.8.2 FIFO Operation

When a complete word has been received, it is transferred to the receive FIFO at the current location of

the Receive FIFO Write Pointer (RWP). After that, the RWP is automatically incremented by 1. Therefore,

data received in the next slot is copied to the next higher FIFO location.

A read from the Audio Receive FIFO Register (ARFR) results in a read from the receive FIFO at the

current location of the Receive FIFO Read Pointer (RRP). After every read operation from the receive

FIFO, the RRP is automatically incremented by 1.

When the RRP is equal to the RWP and the last access to the FIFO was a transfer to the ARFR, the

receive FIFO is full. When a new complete data word has been shifted into the ARSR while the receive

FIFO was already full, the shift register overruns. In this case, the new data in the ARSR will not be

transferred to the FIFO and the RWP will not be incremented. A receive FIFO overrun is indicated by the

RXO bit in the Audio Interface Receive Status and Control Register (ARSCR). No receive interrupt will be

generated (even if enabled).

When the current RWP is equal to the TWP and the last access to the receive FIFO was a read from

ARFR, a receive FIFO underrun has occurred. This error condition is not prevented by hardware. Software

must ensure that no receive underrun occurs.

Advanced Audio Interface

231

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