CP3SP33SMSSLASHNOPB datasheet(227/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

Because four of the six AAI DMA requests can be handled by either the CPU or DSP DMA controllers,

these DMA requests are passed through the Audio Subsystem Controller (ASC), which is programmed to

route them to the DMA controller. To use these AAI DMA requests, they must be enabled at three levels:

•

AAI module—the DMA requests must be enabled in the ADMACR register.

•

ASC module—the AAI DMA requests are assigned to ASC DMA channels 6 (ARDR0), 7 (ATDR0), 8

(ARDR1), and 9 (ATDR1). These channels are controlled by bits 6, 7, 8, and 9 in the ASCDMASEL0

DMA controller. If the DSP DMA controller is selected, the DSP DMA channel must be enabled in the

ASCDDMASELn registers.

•

DMA controller—the DMA request must be enabled in the DMA controller. For the CPU DMA

controller, these are DMA requests 6 (ARDR0), 7 (ATDR0), 8 (ARDR1), and 9 (ATDR1).

24.3 Bit Clock Generation

An 8-bit prescaler is provided to divide the audio interface input clock down to the required bit clock rate.

Software can choose between two input clock sources, Auxiliary Clock 1 and Auxiliary Clock 8.

The input clock is divided by the value of the prescaler BCPRS7:0 + 1 to generate the bit clock.

The bit clock rate fbit can be calculated by the following equation:

fbit = n × fSample × Data Length

n = Number of Slots per Frame

fSample = Sample Frequency in Hz

Data Length = Length of data word in multiples of 8 bits

The ideal required prescaler value Pideal can be calculated as follows:

Pideal = fAudio In / fbit

fAudio In = Source Clock Frequency in Hz

The real prescaler must be set to an integer value, which should be as close as possible to the ideal

prescaler value, to minimize the bit clock error, fbit_error.

fbit_error [%] = (fbit – fAudio In/Preal) / fbit × 100

Advanced Audio Interface

227

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