CP3SP33SMSSLASHNOPB datasheet(228/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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Example:

The audio interface is used to transfer 13-bit linear PCM data for one audio channel at a sample rate of 8k

samples per second. The input clock of the audio interface is 12MHz. Furthermore, the codec requires a

minimum bit clock of 256 kHz to operate properly. Therefore, the number of slots per frame must be set to

2 (network mode) although actually only one slot (slot 0) is used. The codec and the audio interface will

put their data transmit pins in TRI-STATE mode after the PCM data word has been transferred. The

required bit clock rate fbit can be calculated by the following equation:

fbit = n × fSample × Data Length = 2 × 8 kHz × 16 = 256 kHz

The ideal required prescaler value Pideal can be calculated as follows:

Pideal = fAudio In / fbit = 12 MHz / 256 kHz = 46.875

Therefore, the real prescaler value is 47. This results in a bit clock error equal to:

fbit_error = (fbit – fAudio In/Preal)/fbit × 100 = (256 kHz – 12 MHz/47) / 256 kHz × 100 = 0.27%

24.4 Frame Clock Generation

The clock for the frame synchronization signals is derived from the bit clock of the audio interface. A 7-bit

prescaler is used to divide the bit clock to generate the frame sync clock for the receive and transmit

operations. The bit clock is divided by FCPRS + 1. In other words, the value software must write into the

ACCR.FCPRS field is equal to the bit number per frame minus one. The frame may be longer than the

valid data word but it must be equal to or larger than the 8-bit or 16-bit word. Even if 13-, 14-, or 15-bit

data is being used, the frame width must always be at least 16 bits wide.

In addition, software can specify the length of a long frame sync signal. A long frame sync signal can be

either 6, 13, 14, 15, or 16 bits long, depending on the external codec being used. The frame sync length

can be configured by the Frame Sync Length field (FSL) in the AGCR register.

24.5 Audio Interface Operation

24.5.1 Clock Configuration

An auxiliary clock (generated by the Clock module described in Section 14.7) must be configured to

provide a 12 MHz input clock as a time base for the AAI module. The CSS bit in the ACCR register

selects whether the input clock is Auxiliary Clock 1 or Auxiliary Clock 8.

24.5.2 Interrupts

The interrupt logic of the AAI combines up to four interrupt sources and generates one interrupt request

signal to the Interrupt Control Unit (ICU).

The four interrupt sources are:

•

RX FIFO Overrun – AISCR.RXEIP = 1

•

RX FIFO Almost Full (Warning Level) – AISCR.RXIP = 1

•

TX FIFO Under run – AISCR.TXEIP = 1

•

TX FIFO Almost Empty (Warning Level) – AISCR.TXIP=1

In addition to the dedicated input to the ICU for handling these interrupt sources, the Serial Frame Sync

(SFS) signal is the WUI26 input to the MIWU (see Section 17), which can be programmed to assert edge-

triggered interrupts.

Figure 24-6 shows the interrupt structure of the AAI.

228

Advanced Audio Interface

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