CP3SP33SMSSLASHNOPB datasheet(232/407 Pages) TI1

232 / 407 page

Long Frame

Sync Pulse

Bit Shift Clock

(SCK/SRCLK)

Shift Data

(STD/SRD)

DS156

Short Frame

Sync Pulse

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

The receive frame synchronization pulse on the SRFS pin (or SFS in synchronous mode) and the receive

shift clock on the SRCLK (or SCK in synchronous mode) may be generated internally, or they can be

supplied by an external source.

24.6 Communication Options

24.6.1 Data Word Length

The word length of the audio data can be selected to be either 8 or 16 bits. In 16-bit mode, all 16 bits of

the transmit and receive shift registers (ATSR and ARSR) are used. In 8-bit mode, only the lower 8 bits of

the transmit and receive shift registers (ATSR and ARSR) are used.

24.6.2 Frame Sync Signal

The audio interface can be configured to use either long or short frame sync signals to mark the beginning

of a new data frame. If the corresponding Frame Sync Select (FSS) bit in the Audio Control and Status

length of one bit shift clock period. When these short frame sync pulses are used, the transfer of the first

data bit or the first slot begins at the first positive edge of the shift clock after the negative edge on the

frame sync pulse.

If the corresponding Frame Sync Select (FSS) bit in the Audio Control and Status register is set, the

receive and/or transmit path generates or recognizes long frame sync pulses. For 8-bit data, the frame

sync pulse generated will be 6 bit shift clock periods long, and for 16-bit data the frame sync pulse can be

configured to be 13, 14, 15, or 16 bit shift clock periods long. When receiving frame sync, it should be

active on the first bit of data and stay active for a least two bit clock periods. It must go low for at least one

bit clock period before starting a new frame. When long frame sync pulses are used, the transfer of the

first word (first slot) begins at the first positive edge of the bit shift clock after the positive edge of the

frame sync pulse. Figure 24-7 shows examples of short and long frame sync pulses.

Figure 24-7. Short and Long Frame Sync Pulses

Some codecs require an inverted frame sync signal. This is available by setting the Inverted Frame Sync

bit in the AGCR register.

232

Advanced Audio Interface

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB bảng dữ liệu(PDF) 232 Page - Texas Instruments