CP3SP33SMSSLASHNOPB datasheet(238/407 Pages) TI1

238 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

CRF

The Clear Receive FIFO bit is used to clear the receive FIFO. When this bit is written with a 1,

all pointers of the receive FIFO are set to their reset state. After updating the pointers, the CRF

bit will automatically be cleared again.

0 – Writing 0 has no effect.

1 – Writing 1 clears the receive FIFO.

CTF

The Clear Transmit FIFO bit is used to clear the transmit FIFO. When this bit is written with a 1,

all pointers of the transmit FIFO are set to their reset state. After updating the pointers, the CTF

bit will automatically be cleared again.

0 – Writing 0 has no effect.

1 – Writing 1 clears the transmit FIFO.

FSL

The Frame Sync Length field specifies the length of the frame synchronization signal, when a

long frame sync signal (FSS = 1) and a 16-bit data word length

(DWL = 1) are used. If an 8-bit data word length is used, long frame syncs are always 6 bit

clocks in length.

FSL

FRAME SYNC LENGTH

13 bit clocks

14 bit clocks

15 bit clocks

16 bit clocks

IFS

The Inverted Frame Sync bit controls the polarity of the frame sync signal.

0 – Active-high frame sync signal.

1 – Active-low frame sync signal.

IOME

The IOM-2 Mode bit selects the normal PCM interface mode or a special IOM-2 mode used to

connect to external ISDN controller devices. The AAI can only operate as a slave in the IOM-2

mode, i.e. the bit clock and frame sync signals are provided by the ISDN controller. If the IOM2

bit is clear, the AAI operates in the normal PCM interface mode used to connect to external

PCM codecs and other PCM audio devices.

0 – IOM-2 mode disabled.

1 – IOM-2 mode enabled.

AAIEN

The AAI Enable bit controls whether the Advanced Audio Interface is enabled. When the AAI is

disabled, all AAI registers remain accessible.

0 – AAI module disabled.

1 – AAI module enabled.

CLKEN

The Clock Enable bit controls whether the Advanced Audio Interface clock is enabled. The

CLKEN bit must be set to allow access to any AAI register. It must also be set before any other

bit of the AGCR can be set. The CLKEN bit is clear after reset.

0 – AAI module clock disabled.

1 – AAI module clock enabled.

24.7.6 Audio Interrupt Status and Control Register (AISCR)

The AISCR register is used to specify the source and the conditions, when the audio interface interrupt is

asserted to the Interrupt Control Unit. It also holds the interrupt pending bits and the corresponding

interrupt clear bits for each audio interface interrupt source. The APB bus master has read/ write access to

the AISCR register. After reset, this register is clear.

TXEIP

TXIP

RXEIP

RXIP

TXEIE

TXIE

RXEIE

RXIE

Reserved

TXEIC

TXIC

RXEIC

RXIC

238

Advanced Audio Interface

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB bảng dữ liệu(PDF) 238 Page - Texas Instruments

CP3SP33SMS/NOPB bảng dữ liệu(HTML) 238 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL