CP3SP33SMSSLASHNOPB datasheet(240/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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24.7.7 Audio Receive Status and Control Register (ARSCR)

The ARSCR register is used to control the operation of the receiver path of the audio interface. It also

holds bits which report the current status of the receive FIFO. The APB bus master has read/write access

to the ARSCR register. At reset, this register is cleared to 0000h, but after enabling the AAI clock it

becomes 0004h.

12 11

8 7

RXFWL

RXDSA

RXSA

RXO

RXE

RXF

RXAF

The Receive Buffer Almost Full bit is set when the number of data bytes/words in the receive

buffer is equal to the specified warning limit.

0 – Receive FIFO below warning limit.

1 – Receive FIFO is almost full.

RXF

The Receive Buffer Full bit is set when the receive buffer is full. The RXF bit is set when the

RWP is equal to the RRP and the last access was a write to the FIFO.

0 – Receive FIFO is not full.

1 – Receive FIFO full.

RXE

The Receive Buffer Empty bit is set when the RRP is equal to the RWP and the last access to

the FIFO was a read operation (read from ARDR).

0 – Receive FIFO is not empty.

1 – Receive FIFO is empty.

RXO

The Receive Overflow bit indicates that a receive shift register has overrun. This occurs, when

a completed data word has been shifted into ARSR, while the receive FIFO was already full

(the RXF bit was set). In this case, the new data in ARSR will not be copied into the FIFO and

the RWP will not be incremented. Also, no receive interrupt and DMA request will generated.

0 – No overflow has occurred.

1 – Overflow has occurred.

RXSA

The Receive Slot Assignment field specifies which slots are recognized by the receiver of the

audio interface. Multiple slots may be enabled. If the frame consists of less than 4 slots, the

RXSA bits for unused slots are ignored. For example, if a frame only consists of 2 slots, RXSA

bits 2 and 3 are ignored. The following table shows the slot assignment scheme.

RXSA BIT

SLOTS ENABLED

RXSA0

RXSA1

RXSA2

RXSA3

After reset the RXSA field is clear, so software must load the correct slot assignment.

RXDSA The Receive DMA Slot Assignment field specifies which slots (audio channels) are supported

by DMA. If the RXDSA bit is set for an assigned slot (RXSAn = 1), the data received within this

slot will not be transferred into the receive FIFO, but will instead be written into the

corresponding Receive DMA data register (ARDRn). If the ARDRn register is full and the RMA

bit is set, a DMA request is asserted. If the RXSA bit for a slot is clear, the RXDSA bit is

ignored. The following table shows the DMA slot assignment scheme. RXDSA3 must be 0.

RXDSA BIT

SLOTS ENABLED FOR DMA

RXDSA0

RXDSA1

RXDSA2

240

Advanced Audio Interface

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