CP3SP33SMSSLASHNOPB datasheet(241/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

RXFWL The Receive FIFO Warning Level field specifies when a receive interrupt is asserted. A receive

interrupt is asserted, when the number of bytes/words in the receive FIFO is greater than the

warning level value. An RXFWL value of 0 means that a receive interrupt is asserted if one or

more bytes/words are in the RX FIFO. After reset, the RXFWL bit is clear.

24.7.8 Audio Transmit Status and Control Register (ATSCR)

The ATSCR register controls the basic operation of the interface. It also holds bits which report the current

status of the audio communication. The APB bus master has read/ write access to the ATSCR register. At

reset, this register is loaded with F000h, but after enabling the AAI clock it becomes F003h.

12 11

8 7

TXFWL

TXDSA

TXSA

TXU

TXF

TXAF

TXAE

The Transmit FIFO Almost Empty bit is set when the number of data bytes/words in transmit

buffer is equal to the specified warning limit.

0 – Transmit FIFO above warning limit.

1 – Transmit FIFO at or below warning limit.

TXE

The Transmit FIFO Empty bit is set when the transmit buffer is empty. The TXE bit is set to

one every time the TRP is equal to the TWP and the last access to the FIFO was read

operation (into ATSR).

0 – Transmit FIFO not empty.

1 – Transmit FIFO empty.

TXF

The Transmit FIFO Full bit is set when the TWP is equal to the TRP and the last access to the

FIFO was write operation.

0 – Transmit FIFO not full.

1 – Transmit FIFO full.

TXU

The Transmit Underflow bit indicates that the transmit shift register (ATSR) has underrun. This

occurs when the transmit FIFO was already empty and a complete data word has been

transferred. In this case, the TRP will be decremented by 1 and the previous data will be

retransmitted. No transmit interrupt and no DMA request will be generated.

0 – Transmit underrun occurred.

1 – Transmit underrun did not occur.

TXSA

The Transmit Slot Assignment field specifies during which slots the transmitter is active and

drives data through the STD pin. The STD pin is in high impedance state during all other slots.

If the frame consists of less than 4 slots, the TXSA bits for unused slots are ignored. For

example, if a frame only consists of 2 slots, TXSA bits 2 and 3 are ignored. The following table

shows the slot assignment scheme.

TXSA BIT

SLOTS ENABLED

TXSA0

TXSA1

TXSA2

TXSA3

After reset the TXSA field is clear, so software must load the correct slot assignment.

TXDSA

The Transmit DMA Slot Assignment field specifies which slots (audio channels) are supported

by DMA. If the TXDSA bit is set for an assigned slot (TXSAn = 1), the data to be transmitted

within this slot will not be read from the transmit FIFO, but will instead be read from the

corresponding Transmit DMA data register (ATDRn). A DMA request is asserted when the

ATDRn register is empty. If the TXSA bit for a slot is clear, the TXDSA bit is ignored. The

following table shows the DMA slot assignment scheme. TXDSA3 must be 0.

Advanced Audio Interface

241

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