CP3SP33SMSSLASHNOPB datasheet(246/407 Pages) TI1

246 / 407 page

I2SSCK

Left Channel

DS440

I2SSWS

I2SSDI,

I2SSDO

Right Channel

LSB

I2SSCK

Left Channel

DS439

I2SSWS

I2SSDI,

I2SSDO

N-1

Right Channel

N-2

N-3

N-4

MSB

N-2

N-3

N-4

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

Figure 25-2. Left-Justified Format

Figure 25-3 shows the timing of a right-justified data transfer.

Figure 25-3. Right-Justified Format

25.1 Interrupts and DMA

Programmable thresholds are provided for the transmit and receive FIFOs to assert interrupt or DMA

requests when the transmit FIFO can accept new data or the receive FIFO needs to be unloaded.

Because the requests can be handled by either the CPU or DSP interrupt and DMA controllers, the

requests are passed through the Audio Subsystem Controller (ASC). To use the interrupt or DMA

requests, they must be enabled at three levels:

•

I2S Module—the RXLI and RXRI bits in the I2SRXCTL register must be set to enable the receiver

interrupt requests for the left and right channels, respectively. The RXLD and RXRD bits enable the

receiver DMA requests. The TXLI and TXRI bits in the I2STXCTL register enable the transmitter

interrupt requests. The TXLD and TXRD bits enable the transmitter DMA requests.

•

ASC Module—the I2S interrupt is assigned to ASC interrupt channel. Bit 6 in the ASCINTSEL register

must be clear to select CPU interrupt controller or set to select the DSP interrupt controller. The I2S

DMA requests are assigned to ASC DMA channels 14, 15, 16, and 17. For the receiver DMA requests,

ASCDMASEL0 register bits 14 and 15 for the left and right channels, respectively, must be clear to

select CPU DMA controller or set to select the DSP DMA controller. For the transmitter DMA requests,

ASCDMASEL1 register bits 0 and 1 for the left and right channels, respectively, must be clear to select

CPU DMA controller or set to select the DSP DMA controller.

•

Interrupt or DMA Controller—the request must be enabled in the interrupt or DMA controller. For the

CPU interrupt controller, this is interrupt request IRQ26. For the CPU DMA controller, DMA requests 14

and 15 are used by the receiver left and right channels, respectively, and DMA requests 16 and 17 are

used by the transmitter left and right channels.

246

I2S Interface

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