CP3SP33SMSSLASHNOPB datasheet(249/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

RXRI

The Right Channel Receive Interrupt Enable bit enables an interrupt request when the

number of empty words in the right receive FIFO is equal to or less than the receive FIFO

threshold specified in the RXFIFOTHRES field. The status of the interrupt is indicated by

the RXRIRQ bit in the I2SSTAT register.

0 – Interrupt disabled.

1 – Interrupt enabled.

RXLI

The Left Channel Receive Interrupt Enable bit enables an interrupt request when the

number of empty words in the left receive FIFO is equal to or less than the receive FIFO

threshold specified in the RXFIFOTHRES field. The status of the interrupt is indicated by

the RXLIRQ bit in the I2SSTAT register.

0 – Interrupt disabled.

1 – Interrupt enabled.

RXRD

The Right Channel Receive DMA Enable bit enables a DMA request when the number of

empty words in the right receive FIFO is equal to or less than the receive FIFO threshold

specified in the RXFIFOTHRES field. If the interrupt and DMA requests are both enabled

for this condition, only the DMA request is asserted.

0 – DMA disabled.

1 – DMA enabled.

RXLD

The Left Channel Receive DMA Enable bit enables a DMA request when the number of

empty words in the left receive FIFO is equal to or less than the receive FIFO threshold

specified in the RXFIFOTHRES field. If the interrupt and DMA requests are both enabled

for this condition, only the DMA request is asserted.

0 – DMA disabled.

1 – DMA enabled.

RXALIGN

The Receiver Data Alignment field controls the position of the data loaded into the

I2SRXDATALEFT and I2SRXDATARIGHT data registers, as described in Section 25.2.

00 – 24-bit data loaded in upper 3 bytes. Lowest byte cleared.

01 – 24-bit data loaded in lower 3 bytes.

10 – 16-bit data loaded into lower 2 bytes.

11 – 8-bit data loaded into lowest byte.

RXFIFOTH

The Receive FIFO Threshold specifies the number of empty words in the receive FIFOs

RESH

before an interrupt or DMA request is asserted.

RXST

The Receiver Status bit controls whether the I2SSTAT.RXSTATUSR and

I2SSTAT.RXSTATUSL fields indicate the number of empty words in the receive FIFOs

rather than the number of filled words. This field does not affect the interpretation of the

RXFIFOTHRES field or the generation of interrupt and DMA requests.

0 – Status fields indicate the number of filled words in the FIFOs.

1 – Status fields indicate the number of empty words in the FIFOs.

25.3.3 I

2S Transmitter Control Register (I2STXCTL)

The I2STXCTL register is a 32-bit, read/write register that controls the I2S transmitter. At reset, this

TXFIFOENL

TXFIFOENR

TXLD

TXRD

TXLI

TXRI

TXER

TXRES

TXMOD

Reserved

LSBFILL

FLUSH

TXST

Reserved

TXFIFOTHRESH

TXALIGN

249

I2S Interface

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