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CP3SP33SMS/NOPB bảng dữ liệu(PDF) 263 Page - Texas Instruments |
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CP3SP33SMS/NOPB bảng dữ liệu(HTML) 263 Page - Texas Instruments |
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263 / 407 page  CP3SP33 www.ti.com SNOSCW5 – MAY 2013 26.12 CVSD/PCM Converter Registers Table 26-1 lists the CVSD/PCM registers Table 26-1. CVSD/PCM Registers NAME ADDRESS DESCRIPTION CVSDIN0 FF 4800h CVSD Data Input Register 0 CVSDIN1 FF 4C00h CVSD Data Input Register 1 CVSDOUT0 FF 4804h CVSD Data Output Register 0 CVSDOUT1 FF 4C04h CVSD Data Output Register 1 PCMIN0 FF 4808h PCM Data Input Register 0 PCMIN1 FF 4C08h PCM Data Input Register 1 PCMOUT0 FF 480Ch PCM Data Output Register 0 PCMOUT1 FF 4C0Ch PCM Data Output Register 1 LOGIN0 FF 4810h Logarithmic PCM Data Output Register 0 LOGIN1 FF 4C10h Logarithmic PCM Data Output Register 1 LOGOUT0 FF 4814h Logarithmic PCM Data Output Register 0 LOGOUT1 FF 4C14h Logarithmic PCM Data Output Register 1 LINEARIN0 FF 4818h Linear PCM Data Input Register 0 LINEARIN1 FF 4C18h Linear PCM Data Input Register 1 LINEAROUT0 FF 481Ch Linear PCM Data Output Register 0 LINEAROUT1 FF 4C1Ch Linear PCM Data Output Register 1 CVCTRL0 FF 4820h CVSD Control Register 0 CVCTRL1 FF 4C20h CVSD Control Register 1 CVSTAT0 FF 4824h CVSD Status Register 0 CVSTAT1 FF 4C24h CVSD Status Register 1 26.12.1 CVSD Data Input Register n (CVSDINn) The CVSDINn registers are 16-bit, write-only registers. They are used to write CVSD data into the CVSD to PCM converter FIFOs. The FIFOs are 8 words deep. The CVSDIN bit 15 represents the CVSD data bit at t = t0, CVSDIN bit 0 represents the CVSD data bit at t = t0 – 250 µs. 15 0 CVSDIN 26.12.2 CVSD Data Output Register n (CVSDOUTn) The CVSDOUTn registers are 16-bit, read-only registers. They are used to read the CVSD data from the PCM to CVSD converter FIFOs. The FIFOs are 8 words deep. Reading a CVSDOUTn register after reset returns undefined data. 15 0 CVSDOUT 26.12.3 PCM Data Input Register n (PCMINn) The PCMINn registers are 16-bit, write-only registers. They are used to write PCM data to the PCM to CVSD converter via the APB bus. They are double-buffered, providing a 125 µs period for an interrupt or DMA request to respond. Copyright © 2013, Texas Instruments Incorporated Dual CVSD/PCM Conversion Modules 263 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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