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CP3SP33SMS/NOPB bảng dữ liệu(PDF) 271 Page - Texas Instruments |
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CP3SP33SMS/NOPB bảng dữ liệu(HTML) 271 Page - Texas Instruments |
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271 / 407 page ![]() 2 Start Bit 8-Bit Data 1S 2a Start Bit 8-Bit Data 2S 2b Start Bit 8-Bit Data 1S PA 2c Start Bit 8-Bit Data 2S PA DS064 1 Start Bit 7-Bit Data 1S 1a Start Bit 7-Bit Data 2S 1b Start Bit 7-Bit Data 1S PA 1c Start Bit 7-Bit Data 2S PA DS063 CP3SP33 www.ti.com SNOSCW5 – MAY 2013 While in Attention mode, the UART receiver monitors the communication flow but ignores all characters until an ad- dress character is received. On receiving an address character, the contents of the receive shift register are copied to the receive buffer. The URBF bit is set and an interrupt (if enabled) is generated. The UATN bit is automatically cleared, and the UART begins receiving all subsequent characters. Software must examine the contents of the URBUF register and respond by accepting the subsequent characters (by leaving the UATN bit clear) or waiting for the next address character (by setting the UATN bit again). The operation of the UART transmitter is not affected by the selection of this mode. The value of the ninth bit to be transmitted is programmed by setting or clearing the UXB9 bit in the UART Frame Select register. The value of the ninth bit received is read from URB9 in the UART Status Register. 27.2.4 Diagnostic Mode The Diagnostic mode is available for testing of the UART. In this mode, the TXDn and RXDn pins are internally connected together, and data shifted out of the transmit shift register is immediately transferred to the receive shift register. This mode supports only the 9-bit data format with no parity. The number of start and stop bits is programmable. 27.2.5 Frame Format Selection The format shown in Figure 27-4 consists of a start bit, seven data bits (excluding parity), and one or two stop bits. If parity bit generation is enabled by setting the UPEN bit, a parity bit is generated and transmitted following the seven data bits. Figure 27-4. 7-Bit Data Frame Options The format shown in Figure 27-5 consists of one start bit, eight data bits (excluding parity), and one or two stop bits. If parity bit generation is enabled by setting the UPEN bit, a parity bit is generated and transmitted following the eight data bits. Figure 27-5. 8-Bit Data Frame Options Copyright © 2013, Texas Instruments Incorporated Dual/Quad UART 271 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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