CP3SP33SMSSLASHNOPB datasheet(273/407 Pages) TI1

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Interrupt

UERR

UEEI

Interrupt

UTBE

UETI

URBF

UFE

UDOE

UPE

UERI

Interrupt

UDCTS

UEFCI

DS066

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

27.2.7 Interrupts

The UART modules are capable of generating interrupts on:

•

Receive Buffer Full

•

Receive Error

•

Transmit Buffer Empty

•

Clear To Send

Figure 27-7 shows a diagram of the interrupt sources and associated enable bits.

Figure 27-7. UART Interrupts

The interrupts can be individually enabled or disabled using the Enable Transmit Interrupt (UETI), Enable

Receive Interrupt (UERI), and Enable Receive Error Interrupt (UEER) bits in the UnICTRL register.

A transmit interrupt is asserted when both the UTBE and UETI bits are set. To remove this interrupt,

software must either disable the interrupt by clearing the UETI bit or write to the UnTBUF register (which

clears the UTBE bit).

A receive interrupt is asserted on these conditions:

•

Both the URBF and UERI bits are set. To remove this interrupt, software must either disable the

interrupt by clearing the UERI bit or read from the URBUF register (which clears the URBF bit).

•

Both the UERR and the UEEI bits are set. To remove this interrupt, software must either disable the

interrupt by clearing the UEEI bit or read the UnSTAT register (which clears the UERR bit).

A flow control interrupt is asserted when both the UDCTS and the UEFCI bits are set. To remove this

interrupt, software must either disable the interrupt by clearing the UEFCI bit or reading the UnICTRL

Because the UART3 transmit and receive interrupt requests can be handled by either the CPU or DSP

interrupt controllers, the interrupt requests are passed through the Audio Subsystem Controller (ASC),

which must be programmed to route it to the interrupt controller. To use these interrupts, they must be

enabled at three levels:

•

UART3 module—the interrupt must be enabled in the U3ICTRL register.

Dual/Quad UART

273

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