CP3SP33SMSSLASHNOPB datasheet(277/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

UPE

The Parity Error bit indicates whether a parity error is detected within a received character.

This bit is automatically cleared by the hardware when the UnSTAT register is read.

0 – No parity error occurred.

1 – Parity error occurred.

UFE

The Framing Error bit indicates whether the UART fails to receive a valid stop bit at the end of

a frame. This bit is automatically cleared by the hardware when the UnSTAT register is read.

0 – No framing error occurred.

1 – Framing error occurred.

UDOE

The Data Overrun Error bit is set when a new character is received and transferred to the

UnRBUF register before software has read the previous character from the UnRBUF register.

This bit is automatically cleared by the hardware when the UnSTAT register is read.

0 – No receive overrun error occurred.

1 – Receive overrun error occurred.

UERR

The Error Status bit indicates when a parity, framing, or overrun error occurs (any time that

the UPE, UFE, or UDOE bit is set). It is automatically cleared by the hardware when the UPE,

UFE, and UDOE bits are all 0.

0 – No receive error occurred.

1 – Receive error occurred.

UBKD

The Break Detect bit indicates when a line break condition occurs. This condition is detected if

RXDn remains low for at least ten bit times after a missing stop bit has been detected at the

end of a frame. The hardware automatically clears the UBKD bit on reading the UnSTAT

hardware clears the bit as soon as the break condition no longer exists (when the RXDn input

returns to a high level).

0 – No break condition occurred.

1 – Break condition occurred.

URB9

The Received 9th Data Bit holds the ninth data bit, when the UART is configured to operate in

the 9-bit data format.

UXMIP

The Transmit In Progress bit indicates when the UART is transmitting. The hardware sets this

bit when the UART is transmitting data and clears the bit at the end of the last frame bit.

0 – UART is not transmitting.

1 – UART is transmitting.

27.3.3 UART Mode Select Register 1 (UnMDSL1)

The UnMDSL1 registers are 8-bit, read/write registers that select the clock source, synchronization mode,

attention mode, and line break generation. These registers are cleared at reset. The register format is

shown below.

URTS

UFCE

UERD

UETD

UCKS

UBRK

UATN

UMOD

The Mode bit selects between synchronous and asynchronous mode. Synchronous mode is

only available for the UART0 module.

0 – Asynchronous mode.

1 – Synchronous mode.

UATN

The Attention Mode bit is used to enable Attention mode. When set, this bit selects the

attention mode of operation for the UART. When clear, the attention mode is disabled. The

hardware clears this bit after an address frame is received. An address frame is a 9-bit

character with a 1 in the ninth bit position.

0 – Attention mode disabled.

1 – Attention mode enabled.

Dual/Quad UART

277

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