CP3SP33SMSSLASHNOPB datasheet(279/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

UPSC

The Prescaler field specifies the prescaler value used for dividing the PCLK Clock in the first

stage of the two-stage divider chain. For the prescaler factors corresponding to each 5-bit

value, see Table 27-1.

UDIV10:8

The Baud Rate Divisor field holds the three most significant bits (bits 10, 9, and 8) of the

UART baud rate divisor used in the second stage of the two-stage divider chain. The

remaining bits of the baud rate divisor are held in the UnBAUD register.

27.3.6 UART Baud Rate Divisor (UnBAUD)

The UnBAUD registers are 8-bit, read/write registers that contain the lower eight bits of the baud rate

divisor. The register contents are unknown at power-up and are left un- changed by a reset operation. The

UDIV7:0

The Baud Rate Divisor field holds the eight lowest-order bits of the UART baud rate divisor

used in the second stage of the two-stage divider chain. The three most significant bits are

held in the UnPSR register. The divisor value used is (UDIV[10:0] + 1).

27.3.7 UART Frame Select Register (UnFRS)

The UnFRS registers are 8-bit, read/write registers that con- trol the frame format, including the number of

data bits, number of stop bits, and parity type. These registers are cleared at reset. The register format is

shown below.

Reserved

UPEN

UPSEL

UXB9

USTP

UCHAR

The Character Frame Format field selects the number of data bits per frame, not including

the parity bit.

00 – 8 data bits per frame.

01 – 7 data bits per frame.

10 – 9 data bits per frame.

11 – Loop-back mode, 9 data bits per frame.

USTP

The Stop Bits bit specifies the number of stop bits transmitted in each frame.

0 – One stop bit per frame.

1 – Two stop bits per frame.

UXB9

The Transmit 9th Data Bit holds the value of the ninth data bit, either 0 or 1, transmitted

when the UART is configured to transmit nine data bits per frame. It has no effect when the

UART is configured to transmit seven or eight data bits per frame.

UPSEL

The Parity Select field selects the treatment of the parity bit. When the UART is configured

to transmit nine data bits per frame, the parity bit is omitted and the UPSEL field is ignored.

00 – Odd parity.

01 – Even parity.

10 – No parity, transmit 1 (mark).

11 – No parity, transmit 0 (space).

UPEN

The Parity Enable bit enables or disables parity generation and parity checking. When the

UART is configured to transmit nine data bits per frame, there is no parity bit and the

UnPEN bit is ignored.

0 – Parity generation and checking disabled.

1 – Parity generation and checking enabled.

Dual/Quad UART

279

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