CP3SP33SMSSLASHNOPB datasheet(278/407 Pages) TI1

278 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

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UBRK

The Force Transmission Break bit is used to force the TXD output low. Setting this bit to 1

causes the TXD pin to go low. TXD remains low until the UBRK bit is cleared by software.

0 – Normal operation.

1 – TXD pin forced low.

UCKS

The Synchronous Clock Source bit controls the clock source when the UART operates in the

synchronous mode (UMOD = 1). This functionality is only available for the UART0 module. If

the UCKS bit is set, the UART operates from an external clock provided on the CKX pin. If the

UCKS bit is clear, the UART operates from the baud rate clock produced by the UART on the

CKX pin. This bit is ignored when the UART operates in the asynchronous mode.

0 – Internal baud rate clock is used.

1 – External clock is used.

UETD

The Enable Transmit DMA bit controls whether DMA is used for UART transmit operations.

Enabling transmit DMA automatically disables transmit interrupts, without regard to the state of

the UETI bit.

0 – Transmit DMA disabled.

1 – Transmit DMA enabled.

UERD

The Enable Receive DMA bit controls whether DMA is used for UART receive operations.

Enabling receive DMA automatically disables receive interrupts, without regard to the state of

the UERI bit. Receive error interrupts are unaffected by the UERD bit.

0 – Receive DMA disabled.

1 – Receive DMA enabled.

UFCE

The Flow Control Enable bit controls whether flow control interrupts are enabled. This

functionality is only available for the UART0, UART1, and UART2 modules.

0 – Flow control interrupts disabled.

1 – Flow control interrupts enabled.

URTS

The Ready To Send bit directly controls the state of the RTS output. This functionality is only

available for the UART0, UART1, and UART2 modules.

0 – RTS output is high.

1 – RTS output is low.

27.3.4 UART Mode Select Register 2 (UnMDSL2)

The UnMDSL2 registers are 8-bit, read/write registers that control the sample mode used to recover

asynchronous data. At reset, the UnMDSL2 registers are cleared. The register format is shown below.

Reserved

USMD

The USMD bit controls the sample mode for asynchronous transmission.

0 – UART determines the sample position automatically.

1 – The UnSPOS register determines the sample position.

27.3.5 UART Baud Rate Prescaler (UnPSR)

The UnPSR registers are 8-bit, read/write registers that contains the 5-bit clock prescaler and the upper

three bits of the baud rate divisor. These registers are cleared at reset. The register format is shown

below.

3M M2

UPSC

UDIV10:8

278

Dual/Quad UART

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