CP3SP33SMSSLASHNOPB datasheet(274/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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•

ASC module—the UART3 interrupts are assigned to ASC interrupt channels 2 (transmit) and 3

(receive), so bits 2 and 3 in the ASCINTSEL register must be clear to select the CPU interrupt

controller or set to select the DSP interrupt controller.

•

Interrupt controller—the interrupt request must be enabled in the interrupt controller. For the CPU

interrupt controller, these are interrupt requests IRQ12 (transmit) and IRQ13 (receive).

27.2.8 DMA Support

Any UART module can operate with one or two DMA chan- nels. For processor-independent full-duplex

operation, two DMA channels must be used. Both receive and transmit DMA can be enabled

simultaneously.

If transmit DMA is enabled (the UETD bit is set), the UART generates a DMA request when the UTBE bit

changes state from clear to set. Enabling transmit DMA automatically dis- ables transmit interrupts,

without regard to the state of the UETI bit.

If receive DMA is enabled (the UERD bit is set), the UART generates a DMA request when the URBF bit

changes state from clear to set. Enabling receive DMA automatically dis- ables receive interrupts, without

regard to the state of the UERI bit. However, receive error interrupts should be en- abled (the UEEI bit is

set) to allow detection of receive errors when DMA is used.

Because the UART3 DMA requests can be handled by ei- ther the CPU or DSP DMA controllers, the DMA

requests are passed through the Audio Subsystem Controller (ASC), which must be programmed to route

them to the DMA con- troller. To use the UART3 DMA requests, they must be en- abled at three levels:

•

UART3 module—the UART3 DMA requests must be enabled in the U3MDSL1 register.

•

ASC module—the UART3 DMA requests are assigned to ASC DMA channels 0 (receive) and 1

(transmit). These channels are controlled by bits 0 and 1 in the ASCDMASEL0 register. The bits must

be clear to select the CPU DMA controller or set to select the DSP DMA controller. If the DSP DMA

controller is selected, the DSP DMA channel must be programmed in the ASCDDMASELn registers.

•

DMA controller—the DMA requests must be enabled in the DMA controller. For the CPU DMA

controller, these are DMA requests 0 (receive) and 1 (transmit).

27.2.9 Break Generation and Detection

A line break is generated when the UBRK bit is set in the UnMDSL1 register. The TXDn line remains low

until the program resets the UBRK bit.

A line break is detected if RXDn remains low for 10 bit times or longer after a missing stop bit is detected.

27.2.10 Parity Generation and Detection

Parity is only generated or checked with the 7-bit and 8-bit data formats. It is not generated or checked in

the diagnostic loopback mode, the attention mode, or in normal mode with the 9-bit data format. Parity

generation and checking are enabled and disabled using the PEN bit in the UnFRS register. The UPSEL

bits in the UnFRS register are used to select odd, even, or no parity.

27.3 UART Registers

Software interacts with the UART modules by accessing the UART registers, as listed in Table 27-2.

Table 27-2. UART Registers

NAME

ADDRESS

DESCRIPTION

U0ICTRL

FF 9408h

UART0 Interrupt Control Register

U0STAT

FF 940Ch

UART0 Status Register

U0MDSL1

FF 9414h

UART0 Mode Select Register 1

U0MDSL2

FF 9424h

UART0 Mode Select Register 2

274

Dual/Quad UART

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