TMP320C2811PBKA datasheet(124/147 Pages) TI

tên linh kiện	TMP320C2811PBKA

Giải thích chi tiết về linh kiện	TMS320R2811, TMS320R2812 Digital Signal Processors

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Electrical Specifications

124

June 2004

SPRS257

6.27 XHOLD and XHOLDA

If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the

XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of

high-impedance mode.

On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus

and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low.

When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still execute

code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD

signal is removed.

An external DMA request, when granted, places the following signals in a high-impedance mode:

XA[18:0]

XZCS0AND1

XD[15:0]

XZCS2

XWE, XRD

XZCS6AND7

XR/W

All other signals not listed in this group remain in their default or functional operational modes during these

signal events. Detailed timing diagram will be released in a future revision of this data sheet.

TMP320C2811PBKA bảng dữ liệu(PDF) 124 Page - Texas Instruments