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TMP320C2811PBKA bảng dữ liệu(PDF) 125 Page - Texas Instruments

tên linh kiện TMP320C2811PBKA
Giải thích chi tiết về linh kiện  TMS320R2811, TMS320R2812 Digital Signal Processors
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TMP320C2811PBKA bảng dữ liệu(HTML) 125 Page - Texas Instruments

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Electrical Specifications
125
June 2004
SPRS257
6.28 XHOLD/XHOLDA Timing
Table 6−36. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)†‡
MIN
MAX
UNIT
td(HL-HiZ)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
4tc(XTIM)
ns
td(HL-HAL)
Delay time, XHOLD low to XHOLDA low
5tc(XTIM)
ns
td(HH-HAH)
Delay time, XHOLD high to XHOLDA high
3tc(XTIM)
ns
td(HH-BV)
Delay time, XHOLD high to Bus valid
4tc(XTIM)
ns
† When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.
‡ The state of XHOLD is latched on the rising edge of XTIMCLK.
XCLKOUT
(/1 Mode)
XHOLD
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
XD[15:0]
Valid
XHOLDA
td(HL-Hiz)
td(HH-HAH)
High-Impedance
XA[18:0]
Valid
Valid
High-Impedance
td(HH-BV)
td(HL-HAL)
See Note A
See Note B
NOTES: A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6−32. External Interface Hold Waveform



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