TMP320C2811PBKA datasheet(120/147 Pages) TI

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Electrical Specifications

120

June 2004

SPRS257

Lead

Active

Trail

DIN

td(XCOH-XZCSL)

td(XCOH-XA)

td(XCOHL-XRDL)

td(XCOHL-XZCSH)

td(XCOHL-XRDH)

WS (Asynch)

XCLKOUT=XTIMCLK

XCLKOUT=1/2 XTIMCLK

XZCS0AND1, XZCS2,

XZCS6AND7

XA[0:18]

XRD

XWE

XR/W

XD[0:15]

XREADY(Asynch)

NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment

cycle before an access to meet this requirement.

B. During alignment cycles, all signals will transition to their inactive state.

C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment

cycles.

D. For each sample, setup time from the beginning of the access can be calculated as:

D = (XRDLEAD + XRDACTIVE −3 +n) tc(XTIM) − tsu(XRDYasynchL)XCOHL

where n is the sample number: n = 1, 2, 3, and so forth.

E. Reference for the first sample is with respect to this point:

E = (XRDLEAD + XRDACTIVE −2) tc(XTIM)

tsu(XRDYasynchL)XCOHL

tsu(XD)XRD

ta(XRD)

ta(A)

th(XRDYasynchL)

th(XD)XRD

th(XRDYasynchH)XZCSH

= Don’t care. Signal can be high or low during this time.

Legend:

See Notes

A and B

See Note C

tsu(XRDYasynchH)XCOHL

See Note D

See Note E

te(XRDYasynchH)

Figure 6−29. Example Read With Asynchronous XREADY Access

XTIMING register parameters used for this example:

XRDLEAD

XRDACTIVE

XRDTRAIL

USEREADY

X2TIMING

XWRLEAD

XWRACTIVE

XWRTRAIL

READYMODE

≥1

N/A†

1 = XREADY

(Asynch)

† N/A = “Don’t care” for this example

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