AN4088 datasheet(30/71 Pages) STMICROELECTRONICS

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Peripheral migration

AN4088

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DocID023072 Rev 3

I/O pin has a multiplexer with eight alternate function inputs (AF0 to AF7) that can be

configured through the GPIOx_AFRL and GPIOx_AFRH registers:

–

The peripheral alternate functions are mapped by configuring AF0 to AF7.

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate

functions mapped on different I/O pins to optimize the number of peripheral I/O

functions for different device packages. For example, the USART2_RX pin can be

mapped on PA3 or PA15 pin.

Note:

Please refer to the “Alternate function mapping” table in the STM32F0x datasheet for the

detailed mapping of the system and the peripheral alternate function I/O pins.

Configuration procedure

–

Configure the desired I/O as an alternate function in the GPIOx_MODER register

–

Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,

GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively

–

Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register

3.8

EXTI source selection

In STM32F1, the selection of the EXTI line source is performed through EXTIx bits in

AFIO_EXTICRx registers, while in STM32F0 series this selection is done through EXTIx bits

in SYSCFG_EXTICRx registers.

Only the mapping of the EXTICRx registers has been changed, without any changes to the

meaning of the EXTIx bits. However, the maximum range of EXTIx bit values is 0b0101 as

the last PORT is F (in STM32F1 series, the maximum value is 0b0110).

3.9

Flash interface

The table below presents the difference between the Flash interface of STM32F1 series and

STM32F0 series, which can be grouped as follows:



New interface, new technology



New architecture



New read protection mechanism, 3 read protection levels

Consequently, the STM32F0 Flash programming procedures and registers are different

from the STM32F1 series, and any code written for the Flash interface in the STM32F1

series needs to be rewritten to run on STM32F0 series.

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