AN4088 datasheet(28/71 Pages) STMICROELECTRONICS

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Peripheral migration

AN4088

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DocID023072 Rev 3

3.7

GPIO interface

The STM32F0 GPIO peripheral embeds new features compared to STM32F1 series, below

the main features:



GPIO mapped on AHB bus for better performance



I/O pin multiplexer and mapping: pins are connected to on-chip peripherals/modules

through a multiplexer that allows only one peripheral alternate function (AF) connected

to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing

the same I/O pin.



More possibilities and features for I/O configuration

The STM32F0 GPIO peripheral is a new design and thus the architecture, features and

registers are different from the GPIO peripheral in the STM32F1 series. Any code written for

the STM32F1 series using the GPIO needs to be rewritten to run on STM32F0 series.

For more information about STM32F0 GPIO programming and usage, please refer to the

“I/O pin multiplexer and mapping” section in the GPIO chapter of the STM32F0xx Reference

Manual (RM0091).

The table below presents the differences between GPIOs in the STM32F1 series and

STM32F0 series.

DMA2_Channel2

DMA2_Channel3

DMA2_Channel4 / DMA2_Channel4_5

DMA2_Channel5

ETH

ETH_WKUP

CAN2_TX

CAN2_RX0

CAN2_RX1

CAN2_SCE

OTG_FS

1. NA in gray table cells means Not Applicable.

Table 15. Interrupt vector differences between STM32F1 series and STM32F0

series(1) (continued)

Position

STM32F1 series

STM32F0 series

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