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PM0056 bảng dữ liệu(PDF) 133 Page - STMicroelectronics |
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133 / 156 page  DocID15491 Rev 5 133/156 PM0056 Core peripherals 4.4.4 Vector table offset register (SCB_VTOR) Address offset: 0x08 Reset value: 0x0000 0000 Required privilege: Privileged Bits 21:12 VECTPENDING[9:0] Pending vector Indicates the exception number of the highest priority pending enabled exception. 0: No pending exceptions Other values: The exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. Bit 11 RETOBASE: Return to base level Indicates whether there are preempted active exceptions: 0: There are preempted active exceptions to execute 1: There are no active exceptions, or the currently-executing exception is the only active exception. Bits 10:9 Reserved, must be kept cleared Bits 8:0 VECTACTIVE[8:0] Active vector Contains the active exception number: 0: Thread mode Other values: The exception number(1) of the currently active exception. Note: Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, Clear-Pending, Set-Pending, or Priority Registers, see Table 5 on page 18. 1. This is the same value as IPSR bits[8:0], see Interrupt program status register on page 18. 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TBLOFF[29:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 76 54 3 21 0 TBLOFF[15:9] Reserved rw rw rw rw rw rw rw |
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