PIC18F2680ISPSQTP datasheet(130/482 Pages) MICROCHIP

130 / 482 page

PIC18F2585/2680/4585/4680

DS39625C-page 128

Preliminary

9.6

INTn Pin Interrupts

External interrupts on the RB0/INT0, RB1/INT1 and

RB2/INT2 pins are edge-triggered. If the corresponding

INTEDGx bit in the INTCON2 register is set (= 1), the

interrupt is triggered by a rising edge; if the bit is clear,

the trigger is on the falling edge. When a valid edge

appears on the RBx/INTx pin, the corresponding flag

bit INTxF is set. This interrupt can be disabled by clear-

ing the corresponding enable bit INTxE. Flag bit INTxF

must be cleared in software in the Interrupt Service

Routine before re-enabling the interrupt.

All external interrupts (INT0, INT1 and INT2) can

wake-up the processor from the power managed

modes, if bit INTxE was set prior to going into power

managed modes. If the Global Interrupt Enable bit,

GIE, is set, the processor will branch to the interrupt

vector following wake-up.

Interrupt priority for INT1 and INT2 is determined by the

value contained in the interrupt priority bits, INT1IP

(INTCON3<6>) and INT2IP (INTCON3<7>). There is

no priority bit associated with INT0. It is always a high

priority interrupt source.

9.7

TMR0 Interrupt

In 8-bit mode (which is the default), an overflow in the

TMR0 register (FFh

→ 00h) will set flag bit TMR0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L regis-

ter pair (FFFFh

→ 0000h) will set TMR0IF. The interrupt

can be enabled/disabled by setting/clearing enable bit

TMR0IE (INTCON<5>). Interrupt priority for Timer0 is

determined by the value contained in the interrupt

priority bit, TMR0IP (INTCON2<2>). See Section 11.0

“Timer0 Module” for further details on the Timer0

module.

9.8

PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit, RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit, RBIE (INTCON<3>).

Interrupt priority for PORTB interrupt-on-change is

determined by the value contained in the interrupt

priority bit, RBIP (INTCON2<0>).

9.9

Context Saving During Interrupts

During interrupts, the return PC address is saved on

the stack. Additionally, the WREG, STATUS and BSR

registers are saved on the fast return stack. If a fast

return from interrupt is not used (See Section 5.3

“Data Memory Organization”), the user may need to

save the WREG, STATUS and BSR registers on entry

to the Interrupt Service Routine. Depending on the

user’s application, other registers may also need to be

saved. Example 9-1 saves and restores the WREG,

STATUS and BSR registers during an Interrupt Service

Routine.

EXAMPLE 9-1:

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF

W_TEMP

; W_TEMP is in virtual bank

MOVFF

STATUS, STATUS_TEMP

; STATUS_TEMP located anywhere

MOVFF

BSR, BSR_TEMP

; BSR_TMEP located anywhere

;

; USER ISR CODE

;

MOVFF

BSR_TEMP, BSR

; Restore BSR

MOVF

W_TEMP, W

; Restore WREG

MOVFF

STATUS_TEMP, STATUS

; Restore STATUS

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