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PIC18F2680ISPSQTP bảng dữ liệu(PDF) 127 Page - Microchip Technology |
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PIC18F2680ISPSQTP bảng dữ liệu(HTML) 127 Page - Microchip Technology |
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127 / 482 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39625C-page 125 PIC18F2585/2680/4585/4680 REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP(1) — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(2) bit 7 bit 0 bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 =High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit(1) 1 =High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 =High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 =High priority 0 = Low priority bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 =High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 =High priority 0 = Low priority bit 0 ECCP1IP: ECCP1 Interrupt Priority bit(2) 1 =High priority 0 = Low priority Note 1: This bit is available in PIC18F4X8X devices and reserved in PIC18F2X8X devices. 2: This bit is available in PIC18F4X8X devices only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown |
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