Z8F0113 datasheet(56/245 Pages) ZILOG

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PS024315-1011

P R E L I M I N A R Y

GPIO Control Register Definitions

Z8 Encore! XP® F0823 Series

Product Specification

Port A–C Address Registers

The Port A–C Address registers select the GPIO port functionality accessible through the

Port A–C Control registers. The Port A–C Address and Control registers combine to pro-

vide access to all GPIO port controls (Table 19).

PxHDE

High Drive Enable.

PxSMRE

Stop Mode Recovery Source Enable.

PxPUE

Pull-up Enable.

PxAFS1

Alternate Function Set 1.

PxAFS2

Alternate Function Set 2.

Table 19. Port A–C GPIO Address Registers (PxADDR)

Bit

Field

PADDR[7:0]

RESET

00H

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

FD0H, FD4H, FD8H

Bit

Description

[7:0]



PADDR

Port Address

The Port Address selects one of the subregisters accessible through the Port Control Register.

See Table 20 for each subregister function.

Table 20. PADDR[7:0] Subregister Functions

PADDR[7:0]

Port Control Subregister Accessible Using the Port A–C Control Registers

00H

No function. Provides some protection against accidental Port reconfiguration.

01H

Data Direction.

02H

Alternate Function.

03H

Output Control (Open-Drain).

04H

High Drive Enable.

Table 18. GPIO Port Registers and Subregisters (Continued)

Port Register

Mnemonic

Port Register Name

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