Z8F0113 datasheet(85/245 Pages) ZILOG

85 / 245 page

PS024315-1011

P R E L I M I N A R Y

Architecture

Z8 Encore! XP® F0823 Series

Product Specification

Architecture

Figure 9 displays the architecture of the timers.

Operation

The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value

0001H

into the Timer Reload High and Low Byte registers and setting the prescale value

to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload

High and Low Byte registers and setting the prescale value to 128. If the Timer reaches

FFFFH

, the timer rolls over to 0000H and continues counting.

Timer Operating Modes

The timers can be configured to operate in the following modes:

ONE-SHOT Mode

In ONE-SHOT Mode, the timer counts up to the 16-bit reload value stored in the Timer

Reload High and Low Byte registers. The timer input is the system clock. Upon reaching

the reload value, the timer generates an interrupt and the count value in the Timer High

and Low Byte registers is reset to 0001H. The timer is automatically disabled and stops

counting.

Figure 9. Timer Block Diagram

16-Bit

PWM/Compare

16-Bit Counter

with Prescaler

16-Bit

Reload Register

Timer

Control

Interrupt,

PWM,

and

Timer Output

Control

Timer

Timer Block

System

Timer

Data

Block

Output

Control

Bus

Clock

Input

Gate

Input

Capture

Input

Timer

Interrupt

Timer

Output

Complement

Timer

Output

Complement

Z8F0113 bảng dữ liệu(PDF) 85 Page - Zilog, Inc.

Z8F0113 bảng dữ liệu(HTML) 85 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL