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Z8F0113 bảng dữ liệu(PDF) 38 Page - Zilog, Inc. |
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Z8F0113 bảng dữ liệu(HTML) 38 Page - Zilog, Inc. |
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38 / 245 page ![]() PS024315-1011 P R E L I M I N A R Y Reset Sources Z8 Encore! XP® F0823 Series Product Specification 23 Reset Sources Table 10 lists the possible sources of a System Reset. Power-On Reset Each device in the Z8 Encore! XP F0823 Series contains an internal POR circuit. The POR circuit monitors the supply voltage and holds the device in the Reset state until the supply voltage reaches a safe operating level. After the supply voltage exceeds the POR voltage threshold (VPOR), the device is held in the Reset state until the POR Counter has timed out. If the crystal oscillator is enabled by the option bits, this time-out is longer. After the Z8 Encore! XP F0823 Series device exits the POR state, the eZ8 CPU fetches the Reset vector. Following the POR, the POR status bit in Watchdog Timer Control (WDTCTL) Register is set to 1. Figure 5 displays POR operation. For the POR threshold voltage (VPOR), see the Electri- cal Characteristics chapter on page 196. Table 10. Reset Sources and Resulting Reset Type Operating Mode Reset Source Special Conditions NORMAL or HALT modes Power-On Reset/Voltage Brown- Out. Reset delay begins after supply voltage exceeds POR level. Watchdog Timer time-out when configured for Reset. None. RESET pin assertion. All reset pulses less than three system clocks in width are ignored. OCD initiated Reset (OCDCTL[0] set to 1). System Reset, except the OCD is unaffected by the reset. STOP Mode Power-On Reset/Voltage Brown- Out. Reset delay begins after supply voltage exceeds POR level. RESET pin assertion. All reset pulses less than the specified analog delay are ignored. See the Electrical Characteris- tics chapter on page 196. DBG pin driven Low. None. |
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