Z8F0113 datasheet(42/245 Pages) ZILOG

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PS024315-1011

P R E L I M I N A R Y

Stop Mode Recovery

Z8 Encore! XP® F0823 Series

Product Specification

The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H

and loads that value into the Program Counter. Program execution begins at the Reset vec-

tor address. Following Stop Mode Recovery, the STOP bit in the Watchdog Timer Control

The section following the table provides more detailed information about each of the Stop

Mode Recovery sources.

Stop Mode Recovery Using Watchdog Timer Time-Out

If the Watchdog Timer times out during STOP Mode, the device undergoes a Stop Mode

Recovery sequence. In the Watchdog Timer Control Register, the WDT and STOP bits are set

to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and Z8

Encore! XP F0823 Series device is configured to respond to interrupts, the eZ8 CPU services

the Watchdog Timer interrupt request following the normal Stop Mode Recovery sequence.

Stop Mode Recovery Using a GPIO Port Pin Transition

Each of the GPIO port pins can be configured as a Stop Mode Recovery input source. On

any GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value

(from High to Low or from Low to High) initiates Stop Mode Recovery.

The SMR pulses shorter than specified does not trigger a recovery. When this happens, the

STOP bit in the Reset Status (RSTSTAT) Register is set to 1.

In STOP Mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input

Data registers record the port transition only if the signal stays on the port pin through the

end of the Stop Mode Recovery delay. As a result, short pulses on the port pin can initiate

Stop Mode Recovery without being written to the Port Input Data Register or without ini-

tiating an interrupt (if enabled for that pin).

Table 11. Stop Mode Recovery Sources and Resulting Action

Operating Mode Stop Mode Recovery Source

Action

STOP Mode

Watchdog Timer time-out when configured

for Reset

Stop Mode Recovery

Watchdog Timer time-out when configured

for interrupt

Stop Mode Recovery followed by interrupt

(if interrupts are enabled)

Data transition on any GPIO port pin

enabled as a Stop Mode Recovery source

Stop Mode Recovery

Assertion of external RESET Pin

System Reset

Debug Pin driven Low

System Reset

Note:

Caution:

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