Z8F0113 datasheet(25/245 Pages) ZILOG

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PS024315-1011

P R E L I M I N A R Y

Signal Descriptions

Z8 Encore! XP® F0823 Series

Product Specification

COUT

Comparator Output. This is the output of the comparator.

Analog

ANA[7:0]

Analog port. These signals are used as inputs to the ADC. The ANA0,

ANA1, and ANA2 pins can also access the inputs and output of the inte-

grated transimpedance amplifier.

VREF

I/O

Analog-to-Digital Converter reference voltage input.

Clock Input

CLKIN

Clock Input Signal. This pin can be used to input a TTL-level signal to be

used as the system clock.

LED Drivers

LED

Direct LED drive capability. All port C pins have the capability to drive an

LED without any other external components. These pins have programma-

ble drive strengths set by the GPIO block.

On-Chip Debugger

DBG

I/O

Debug. This signal is the control and data input and output to and from the

OCD.

Caution: The DBG pin is open-drain and requires an external pull-up

resistor to ensure proper operation.

Reset

RESET

I/O

RESET. Generates a reset when asserted (driven Low). Also serves as a

reset indicator; the Z8 Encore! XP forces this pin Low when in reset. This

pin is open-drain and features an enabled internal pull-up resistor.

Power Supply

VDD

Digital Power Supply.

AVDD

Analog Power Supply.

VSS

Digital Ground.

AVSS

Analog Ground.

Table 3. Signal Descriptions (Continued)

Signal Mnemonic

I/O

Description

Notes:

1. PB6 and PB7 are only available in 28-pin packages without ADC. In 28-pin packages with ADC, they are

replaced by AVDD and AVSS.

2. The AVDD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and

PB7 on 28-pin packages without ADC.

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