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PS024315-1011

P R E L I M I N A R Y

Reset Register Definitions

Z8 Encore! XP® F0823 Series

Product Specification

Stop Mode Recovery Using the External RESET Pin

When a Z8 Encore! XP F0823 Series device is in STOP Mode and the external RESET pin

is driven Low, a system reset occurs. Because of a glitch filter operating on the RESET

pin, the Low pulse must be greater than the minimum width specified, or it is ignored. For

more details, see the Electrical Characteristics chapter on page 196.

Reset Register Definitions

The following sections define the Reset registers.

Reset Status Register

The Reset Status (RSTSTAT) Register is a read-only register that indicates the source of

the most recent Reset event, indicates a Stop Mode Recovery event, and indicates a

Watchdog Timer time-out. Reading this register resets the upper four bits to 0.

This register shares its address with the Watchdog Timer Control Register, which is write-

only; see Table 12.

Table 12. Reset Status Register (RSTSTAT)

Bit

Field

POR

STOP

WDT

EXT

Reserved

RESET

See descriptions in Table 13

00000

R/W

RRRRRRR

Address

FF0H

Bit

Description

[7]



POR

Power-On Reset Indicator

If this bit is set to 1, a Power-On Reset event has occurred. This bit is reset to 0 if a WDT time-

out or Stop Mode Recovery occurs. This bit is also reset to 0 when the register is read. For

POR/Stop Mode Recover event values, please see Table 13.

[6]



STOP

Stop Mode Recovery Indicator

If this bit is set to 1, a Stop Mode Recovery is occurred. If the STOP and WDT bits are both set

to 1, the Stop Mode Recovery occurred because of a WDT time-out. If the STOP bit is 1 and

the WDT bit is 0, the Stop Mode Recovery was not caused by a WDT time-out. This bit is reset

by a POR or a WDT time-out that occurred while not in STOP Mode. Reading this register also

resets this bit. For POR/Stop Mode Recover event values, please see Table 13.

[5]



WDT

Watchdog Timer Time-Out Indicator

If this bit is set to 1, a WDT time-out has occurred. A POR resets this pin. A Stop Mode Recov-

ery from a change in an input pin also resets this bit. Reading this register resets this bit; this

read must occur before clearing the WDT interrupt. For POR/Stop Mode Recover event values,

please see Table 13.

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