STM32F101X8_10 datasheet(17/85 Pages) STMICROELECTRONICS

17 / 85 page

STM32F101x8, STM32F101xB

Description

Doc ID 13586 Rev 13

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than the VPVD threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

Refer to Table 10: Embedded reset and power control block characteristics for the values of

VPOR/PDR and VPVD.

2.3.11

Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

●

MR is used in the nominal regulation mode (Run)

●

LPR is used in the Stop mode

●

Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high

impedance output.

2.3.12

Low-power modes

The STM32F101xx medium-density access line supports three low-power modes to achieve

the best compromise between low power consumption, short startup time and available

wakeup sources:

●

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

●

Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output or the RTC alarm.

●

Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.13

DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management avoiding the generation of interrupts when the controller

reaches the end of the buffer.

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