STM32F101X8_10 datasheet(56/85 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F101x8, STM32F101xB

56/85

Doc ID 13586 Rev 13

Output voltage levels

Unless otherwise specified, the parameters given in Table 34 are derived from tests

performed under the ambient temperature and VDD supply voltage conditions summarized

in Table 8. All I/Os are CMOS and TTL compliant.

Table 34.

Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

VOL

(1)

The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6

and the sum of IIO (I/O ports and control pins) must not exceed IVSS.

Output Low level voltage for an I/O pin

when 8 pins are sunk at the same time

TTL port,

IIO = +8 mA,

2.7 V < VDD < 3.6 V

0.4

VOH

(2)

The IIO current sourced by the device must always respect the absolute maximum rating specified in

Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.

Output High level voltage for an I/O pin

when 8 pins are sourced at the same time

VDD–0.4

VOL

(1)

Output low level voltage for an I/O pin

when 8 pins are sunk at the same time

CMOS port

IIO = +8 mA

2.7 V < VDD < 3.6 V

0.4

VOH

(2)

Output high level voltage for an I/O pin

when 8 pins are sourced at the same time

2.4

VOL

(1)

Output low level voltage for an I/O pin

when 8 pins are sunk at the same time

IIO = +20 mA

(3)

2.7 V < VDD < 3.6 V

Based on characterization data, not tested in production.

1.3

VOH

(2)

Output high level voltage for an I/O pin

when 8 pins are sourced at the same time

VDD–1.3

VOL

(1)

Output low level voltage for an I/O pin

when 8 pins are sunk at the same time

IIO = +6 mA

(3)

2 V < VDD < 2.7 V

0.4

VOH

(2)

Output high level voltage for an I/O pin

when 8 pins are sourced at the same time

VDD–0.4

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