HCS12 datasheet(318/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

318

Freescale Semiconductor

CPU12, the stacked return address can be used to calculate the address of

the unimplemented opcode for software-controlled traps.

7.7 Software Interrupt Instruction (SWI)

Execution of the SWI instruction causes an interrupt without an interrupt

service request. SWI is not inhibited by the global mask bits in the CCR, and

execution of SWI sets the I mask bit. Once an SWI interrupt begins,

maskable interrupts are inhibited until the I bit in the CCR is cleared. This

typically occurs when an RTI instruction at the end of the SWI service

routine restores context.

7.8 Exception Processing Flow

The first cycle in the exception processing flow for all CPU12 exceptions is

the same, regardless of the source of the exception. Between the first and

second cycles of execution, the CPU chooses one of three alternative

paths. The first path is for resets, the second path is for pending X or I

interrupts, and the third path is used for software interrupts (SWI) and

trapping unimplemented opcodes. The last two paths are virtually identical,

differing only in the details of calculating the return address. Refer to Figure

7-1 for the following discussion.

7.8.1 Vector Fetch

The first cycle of all exception processing, regardless of the cause, is a

vector fetch. The vector points to the address where exception processing

will continue. Exception vectors are stored in a table located at the top of the

memory map ($FFxx). The CPU cannot use the fetched vector until the third

cycle of the exception processing sequence.

During the vector fetch cycle, the CPU issues a signal that tells the interrupt

module to drive the vector address of the highest priority, pending exception

onto the system address bus (the CPU does not provide this address).

After the vector fetch, the CPU selects one of the three alternate execution

paths, depending upon the cause of the exception.

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