HCS12 datasheet(314/452 Pages) FREESCALE

314 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

314

Freescale Semiconductor

Power-on reset (POR) and external reset share the same reset vector. The

computer operating properly (COP) reset and the clock monitor reset each

have a vector.

7.4.1 Power-On Reset

The HCS12 incorporate circuitry to detect a positive transition in the VDD

supply and initialize the device during cold starts, generally by asserting the

reset signal internally. The signal is typically released after a delay that

allows the device clock generator to stabilize.

7.4.2 External Reset

The MCU distinguishes between internal and external resets by sensing

how quickly the signal on the RESET pin rises to logic level 1 after it has

been asserted. When the MCU senses any of the four reset conditions,

internal circuitry drives the RESET signal low for N clock cycles, then

releases. M clock cycles later, the MCU samples the state of the signal

applied to the RESET pin. If the signal is still low, an external reset has

occurred. If the signal is high, reset is assumed to have been initiated

internally by either the COP system or the clock monitor.

7.4.3 COP Reset

The MCU includes a computer operating properly (COP) system to help

protect against software failures. When the COP is enabled, software must

write a particular code sequence to a specific address to keep a watchdog

timer from timing out. If software fails to execute the sequence properly, a

reset occurs.

7.4.4 Clock Monitor Reset

The clock monitor circuit uses an internal RC circuit to determine whether

clock frequency is above a predetermined limit. If clock frequency falls

below the limit when the clock monitor is enabled, a reset occurs.

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