TDA9983BHWSLASH8SLASHC1 datasheet(103/119 Pages) NXP

103 / 119 page

TDA9983B_1

Product data sheet

Rev. 01 — 20 May 2008

103 of 119

NXP Semiconductors

TDA9983B

150 MHz pixel rate HDMI transmitter

13. Dynamic characteristics

Table 115. Timing characteristics

VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V;

VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 °C to 70 °C.

Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V

and Tamb = 25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies: pins VDDC(1V8), VDDD(3V3); see Figure 14

delay time

Clock inputs: pins VCLK, VPA[7:0], VPB[7:0], VPC[7:0]; see Figure 15, 16, 17, 18 and 19

fclk(max)

maximum clock frequency

TDA9983BHW/8

MHz

TDA9983BHW/15

150

MHz

tsu(D)

data input set-up time

−1.3

th(D)

data input hold time

3.6

δclk

clock duty cycle

DDC I2C-bus; 5 V tolerant; master bus: pins DDC_SDA and DDC_SCL

fSCL

SCL clock frequency

standard mode

100

kHz

I2C-bus; 5 V tolerant; master bus: pins I2C_SDA and I2C_SCL

fSCL

SCL clock frequency

standard mode

100

kHz

fast mode

400

kHz

TMDS output pins: TXC

− and TXC+

fclk(max)

maximum clock frequency

TDA9983BHW/8

MHz

TDA9983BHW/15

150

MHz

TMDS output pins: TX0

−, TX0+, TX1−, TX1+, TX2− and TX2+

fclk(max)

maximum clock frequency

TDA9983BHW/8

810

MHz

TDA9983BHW/15

1.5

GHz

Fig 14. Power supply sequencing

001aag259

50 %

27 %

td ≥ 0 s

1.8 V

3.3 V

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