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TDA9983BHW/8/C1 bảng dữ liệu(PDF) 92 Page - NXP Semiconductors |
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TDA9983BHW/8/C1 bảng dữ liệu(HTML) 92 Page - NXP Semiconductors |
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92 / 119 page  TDA9983B_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 20 May 2008 92 of 119 NXP Semiconductors TDA9983B 150 MHz pixel rate HDMI transmitter 22h ISRC1_RSVD 7 to 0 ISRC1_RSVD[7:0] R/W 00h* ISRC1 reserved: reserved (shall be zero) ISRC1 data byte x: x = 0 to 15 23h UPC_EAN_ISRC_0 7 to 0 UPC_EAN_ISRC_0[7:0] R/W 00h* UPC/EAN or ISRC byte 0 24h UPC_EAN_ISRC_1 7 to 0 UPC_EAN_ISRC_1[7:0] R/W 00h* UPC/EAN or ISRC byte 1 25h UPC_EAN_ISRC_2 7 to 0 UPC_EAN_ISRC_2[7:0] R/W 00h* UPC/EAN or ISRC byte 2 26h UPC_EAN_ISRC_3 7 to 0 UPC_EAN_ISRC_3[7:0] R/W 00h* UPC/EAN or ISRC byte 3 27h UPC_EAN_ISRC_4 7 to 0 UPC_EAN_ISRC_4[7:0] R/W 00h* UPC/EAN or ISRC byte 4 28h UPC_EAN_ISRC_5 7 to 0 UPC_EAN_ISRC_5[7:0] R/W 00h* UPC/EAN or ISRC byte 5 29h UPC_EAN_ISRC_6 7 to 0 UPC_EAN_ISRC_6[7:0] R/W 00h* UPC/EAN or ISRC byte 6 2Ah UPC_EAN_ISRC_7 7 to 0 UPC_EAN_ISRC_7[7:0] R/W 00h* UPC/EAN or ISRC byte 7 2Bh UPC_EAN_ISRC_8 7 to 0 UPC_EAN_ISRC_8[7:0] R/W 00h* UPC/EAN or ISRC byte 8 2Ch UPC_EAN_ISRC_9 7 to 0 UPC_EAN_ISRC_9[7:0] R/W 00h* UPC/EAN or ISRC byte 9 2Dh UPC_EAN_ISRC_10 7 to 0 UPC_EAN_ISRC_10[7:0] R/W 00h* UPC/EAN or ISRC byte 10 2Eh UPC_EAN_ISRC_11 7 to 0 UPC_EAN_ISRC_11[7:0] R/W 00h* UPC/EAN or ISRC byte 11 2Fh UPC_EAN_ISRC_12 7 to 0 UPC_EAN_ISRC_12[7:0] R/W 00h* UPC/EAN or ISRC byte 12 30h UPC_EAN_ISRC_13 7 to 0 UPC_EAN_ISRC_13[7:0] R/W 00h* UPC/EAN or ISRC byte 13 31h UPC_EAN_ISRC_14 7 to 0 UPC_EAN_ISRC_14[7:0] R/W 00h* UPC/EAN or ISRC byte 14 32h UPC_EAN_ISRC_15 7 to 0 UPC_EAN_ISRC_15[7:0] R/W 00h* UPC/EAN or ISRC byte 15 ISRC1 data byte x: x = 16 to 27 33h ISRC1_PB16 7 to 0 ISRC1_PB_BYTE_16[7:0] R/W 00h* reserved byte 16 (shall be set to a value of 0) 34h ISRC1_PB17 7 to 0 ISRC1_PB_BYTE_17[7:0] R/W 00h* reserved byte 17 (shall be set to a value of 0) 35h ISRC1_PB18 7 to 0 ISRC1_PB_BYTE_18[7:0] R/W 00h* reserved byte 18 (shall be set to a value of 0) 36h ISRC1_PB19 7 to 0 ISRC1_PB_BYTE_19[7:0] R/W 00h* reserved byte 19 (shall be set to a value of 0) 37h ISRC1_PB20 7 to 0 ISRC1_PB_BYTE_20[7:0] R/W 00h* reserved byte 20 (shall be set to a value of 0) 38h ISRC1_PB21 7 to 0 ISRC1_PB_BYTE_21[7:0] R/W 00h* reserved byte 21 (shall be set to a value of 0) 39h ISRC1_PB22 7 to 0 ISRC1_PB_BYTE_22[7:0] R/W 00h* reserved byte 22 (shall be set to a value of 0) 3Ah ISRC1_PB23 7 to 0 ISRC1_PB_BYTE_23[7:0] R/W 00h* reserved byte 23 (shall be set to a value of 0) 3Bh ISRC1_PB24 7 to 0 ISRC1_PB_BYTE_24[7:0] R/W 00h* reserved byte 24 (shall be set to a value of 0) 3Ch ISRC1_PB25 7 to 0 ISRC1_PB_BYTE_25[7:0] R/W 00h* reserved byte 25 (shall be set to a value of 0) 3Dh ISRC1_PB26 7 to 0 ISRC1_PB_BYTE_26[7:0] R/W 00h* reserved byte 26 (shall be set to a value of 0) 3Eh ISRC1_PB27 7 to 0 ISRC1_PB_BYTE_27[7:0] R/W 00h* reserved byte 27 (shall be set to a value of 0) Table 103. ISRC1 packet registers (address 20h to 3Eh) bit description …continued Legend: * = default value Address Register Bit Symbol Access Value Description |
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