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TDA9983BHW/8/C1 bảng dữ liệu(PDF) 43 Page - NXP Semiconductors

tên linh kiện TDA9983BHW/8/C1
Giải thích chi tiết về linh kiện  HDMI transmitter up to 150 MHz pixel rate with 3 쨈 8-bit video inputs and 4 쨈 I2S-bus with S/PDIF
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TDA9983B_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 20 May 2008
43 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
9.3.10 Current page address register
9.4 Scaler page register definitions
The current page address for the Scaler page is 01h.
The configuration of the registers for this page is given in Table 51.
F2h
TRAIL_OFF
7 to 4
x
W
0000*
undefined
3 to 0
TRAIL_OFFSET[3:0]
W
0010*
trailing offset: trailing offset for dwin (in
case rpt > 1)
F9h
GHOST_XADDR
7 to 1
GHOST_XADDR[6:0] W
0110
000*
ghost extended address
0
A0_ZERO
W
0*
-
FDh
AIP_CLKSEL
7 to 5
x
W
000*
undefined
4 to 3
SEL_AIP[1:0]
W
selection audio input
00*
S/PDIF
01
I2S-bus
1X
for internal use
2
SEL_POL_CLK
W
0*
select polarity clock: for internal use
1 to 0
SEL_FS[1:0]
W
select fs: CTS reference
00*
aclk
01
mclk
1X
fs_64 (S/PDIF)
FEh
GHOST_ADDR
7 to 1
GHOST_ADDR[6:0]
W
1010
000*
ghost address
0
GHOST_DIS
W
1*
-
Table 49.
Control registers (address F0h to F2h, F9h, FDh and FEh) bit description …continued
Legend: * = default value
Address
Register
Bit
Symbol
Access Value
Description
Table 50.
CURPAGE_ADR register (address FFh) bit description
Legend: * = default value
Bit
Symbol
Access
Value
Description
7 to 0
CURPAGE_ADR[7:0]
W
00h*
current page address: selects the
current memory page



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