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TDA9983BHW/8/C1 bảng dữ liệu(PDF) 38 Page - NXP Semiconductors |
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TDA9983BHW/8/C1 bảng dữ liệu(HTML) 38 Page - NXP Semiconductors |
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38 / 119 page  TDA9983B_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 20 May 2008 38 of 119 NXP Semiconductors TDA9983B 150 MHz pixel rate HDMI transmitter Table 37. HS_PIX_xx registers (address B9h to BCh) bit description Legend: * = default value Address Register Bit Symbol Access Value Description B9h HS_PIX_START_MSB 7 to 5 x W 000* undefined 4 to 0 HS_PIX_START[12:8] W 0 0000* horizontal synchronization pixel number for start pulse in field 1 BAh HS_PIX_START_LSB 7 to 0 HS_PIX_START[7:0] W 00h* BBh HS_PIX_STOP_MSB 7 to 5 x W 000* undefined 4 to 0 HS_PIX_END[12:8] W 0 0000* horizontal synchronization pixel number for end pulse in field 2 BCh HS_PIX_STOP_LSB 7 to 0 HS_PIX_END[7:0] W 00h* Table 38. VWIN_START_xx and VWIN_END_xx registers (address BDh and C4h) bit description Legend: * = default value Address Register Bit Symbol Access Value Description BDh VWIN_START_1_MSB 7 to 3 x W 0000 0* undefined 2 to 0 VWIN_START_1[10:8] W 000* vertical window start 1: vertical window line number for start pulse in field 1 BEh VWIN_START_1_LSB 7 to 0 VWIN_START_1[7:0] W 00h* BFh VWIN_END_1_MSB 7 to 3 x W 0000 0* undefined 2 to 0 VWIN_END_1[10:8] W 000* vertical window end 1: vertical window line number for end pulse in field 1 C0h VWIN_END_1_LSB 7 to 0 VWIN_END_1[7:0] W 00h* C1h VWIN_START_2_MSB 7 to 3 x W 0000 0* undefined 2 to 0 VWIN_START_2[10:8] W 000* vertical window start 2: vertical window line number for start pulse in field 2 C2h VWIN_START_2_LSB 7 to 0 VWIN_START_2[7:0] W 00h* C3h VWIN_END_2_MSB 7 to 3 x W 0000 0* undefined 2 to 0 VWIN_END_2[10:8] W 000* vertical window end 2: vertical window line number for end pulse in field 2 C4h VWIN_END_2_LSB 7 to 0 VWIN_END_2[7:0] W 00h* Table 39. DE_xxx registers (address C5h to C8h) bit description Legend: * = default value Address Register Bit Symbol Access Value Description C5h DE_START_MSB 7 to 5 x W 000* undefined 4 to 0 DE_START[12:8] W 0 0000* data enable start: data enable pixel number for start pulse in field 1 C6h DE_START_LSB 7 to 0 DE_START[7:0] W 00h* C7h DE_STOP_MSB 7 to 5 x W 000* undefined 4 to 0 DE_END[12:8] W 0 0000* data enable end: data enable pixel number for end pulse in field 2 C8h DE_STOP_LSB 7 to 0 DE_END[7:0] W 00h* Table 40. COLBAR_WIDTH register (address C9h) bit description Legend: * = default value Bit Symbol Access Value Description 7 to 0 CBW[7:0] W 00h* color bar width |
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