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TDA9983BHW/8/C1 bảng dữ liệu(PDF) 89 Page - NXP Semiconductors |
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TDA9983BHW/8/C1 bảng dữ liệu(HTML) 89 Page - NXP Semiconductors |
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89 / 119 page ![]() TDA9983B_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 20 May 2008 89 of 119 NXP Semiconductors TDA9983B 150 MHz pixel rate HDMI transmitter 3 to 2 CTL_CODE[1:0] R/W control code: force CTL[1:0] 00 CTL[1:0] = 00 (DVI mode) 01* CTL[1:0] = 01 (advised to use in case of HDMI mode) 10 CTL[1:0] = 10 (only for debugging purposes) 11 CTL[1:0] = 11 (only for debugging purposes) 1 to 0 DC_CTL[1:0] R/W disparity counter control 00* video guard band initializes disparity_cnt 01 video_data_enable enables disparity_cnt 10 free-running disparity_cnt 11 undefined Table 99. DIP_FLAGS register (address 0Eh) bit description Legend: * = default value Bit Symbol Access Value Description 7 FORCE_NULL R/W force null 0* no specific action 1 insert null-packets continuously 6 NULL R/W null 0* no specific action 1 insert one null-packet (this bit is reset by internal control) 5 - R/W -: data packet header/contents as specified by registers 80h to 9Eh 0* no specific action 1 insert InfoFrame in first free slot after the keepout window 4 ACP R/W audio content protection: data packet header/contents as specified by registers 60h to 7Eh (see Table 105) 0* no specific action 1 insert ’acp’ in first free slot after the keepout window 3 ISRC2 R/W international standard recording code 2: data packet header/contents as specified by registers 40h to 5Eh (see Table 104) 0* no specific action 1 insert ’isrc2’ in first free slot after the keepout window Table 98. ENC_CNTRL register (address 0Dh) bit description …continued Legend: * = default value Bit Symbol Access Value Description |
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