AT89LP6440 datasheet(44/194 Pages) ATMEL

44 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

10. I/O Ports

The AT89LP6440 can be configured for between 35 and 38 I/O pins. The exact number of I/O

pins available depends on the clock and reset options as shown in Table 10-1.

10.1

Port Configuration

All port pins on the AT89LP6440 may be configured to one of four modes: quasi-bidirectional

(standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port modes may

be assigned in software on a pin-by-pin basis as shown in Table 10-2 using the registers listed in

Table 10-3. The Tristate-Port User Fuse determines the default state of the port pins. When the

fuse is enabled, all port pins default to input-only mode after reset. When the fuse is disabled, all

port pins, with the exception of the analog inputs, P0.7-0, P2.4, P2.5, P2.6 and P2.7, default to

quasi-bidirectional mode after reset and are weakly pulled high. The analog input pins always

reset to input-only (tristate) mode. Each port pin also has a Schmitt-triggered input for improved

input noise rejection. During Power-down all the Schmitt-triggered inputs are disabled with the

exception of P3.2 (INT0), P3.3 (INT1), P4.2 (RST), P4.0 (XTAL1) and P4.1 (XTAL2) which may

be used to wake up the device. Therefore, P3.2, P3.3, P4.2, P4.0 and P4.1 should not be left

floating during Power-down. In addition any pin of Port 1 configured as a General-Purpose inter-

rupt input will also remain active during Power-down to wake-up the device. These interrupt pins

should either be disabled before entering Power-down or they should not be left floating.

Table 10-1.

I/O Pin Configurations

Clock Source

Reset Option

Number of I/O Pins

External Crystal or

Resonator

External RST Pin

No external reset

External Clock

External RST Pin

No external reset

Internal RC Oscillator

External RST Pin

No external reset

Table 10-2.

Configuration Modes for Port x, Bit y

PxM0.y

PxM1.y

Port Mode

Quasi-bidirectional

Push-pull Output

Input Only (High Impedance)

Open-Drain Output

Table 10-3.

Port Configuration Registers

Port

Port Data

Port Configuration

0P0 (80H)

P0M0 (BAH), P0M1 (BBH)

P1 (90H)

P1M0 (C2H), P1M1 (C3H)

P2 (A0H)

P2M0 (C4H), P2M1 (C5H)

P3 (B0H)

P3M0 (C6H), P3M1 (C7H)

P4 (C0H)

P4M0 (BEH), P4M1 (BFH)

AT89LP6440 bảng dữ liệu(PDF) 44 Page - ATMEL Corporation

AT89LP6440 bảng dữ liệu(HTML) 44 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL