AT89LP6440 datasheet(38/194 Pages) ATMEL

38 / 194 page

3706A–MICRO–9/09

AT89LP6440 - Preliminary

Figure 8-3.

Reset Recovery from Power-down

8.3.2

Analog Comparators

The comparators will operate during Idle mode if enabled. To save power, the comparators

should be disabled before entering Idle mode if possible. When the comparators are turned off

and on again, some settling time is required for the analog circuits to stabilize. If the comparators

are enabled, they will consume the least power when using an external reference, RFA

1-0 =00B

and RFB

1-0 =00B.

8.3.3

Analog-to-Digital Converter

The DADC will operate during Idle mode if enabled. To save power, the DADC should be dis-

abled before entering Idle mode if possible. When the DADC is turned off and on again, some

settling time is required for the analog circuits to stabilize. If the DADC is enabled, it will con-

sume the least power when configured to use the system clock instead of the internal RC

oscillator (unless the IRC is the system clock source) and when the internal reference is disabled

(IREF = 0). The DADC must always be disabled before entering power-down.

Interrupts

The AT89LP6440 provides 12 interrupt sources: two external interrupts, three timer interrupts, a

serial port interrupt, an analog comparator interrupt, a general-purpose interrupt, a com-

pare/capture interrupt, a two-wire interrupt, an ADC interrupt and an SPI interrupt. These

interrupts and the system reset each have a separate program vector at the start of the program

memory space. Each interrupt source can be individually enabled or disabled by setting or clear-

ing a bit in the interrupt enable registers IE and IE2. The IE register also contains a global

disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or

clearing bits in the interrupt priority registers IP, IPH, IP2 and IP2H. IP and IP2 hold the low order

priority bits and IPH and IP2H hold the high priority bits for each interrupt. An interrupt service

routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of

the same or lower priority. The highest priority interrupt cannot be interrupted by any other inter-

rupt source. If two requests of different priority levels are pending at the end of an instruction, the

request of higher priority level is serviced. If requests of the same priority level are pending at

the end of an instruction, an internal polling sequence determines which request is serviced. The

polling sequence is based on the vector address; an interrupt with a lower vector address has

higher priority than an interrupt with a higher vector address. Note that the polling sequence is

only used to resolve pending requests of the same priority level.

PWD

RST

XTAL1

tSUT

Internal

Clock

Internal

Reset

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